CX28344 Conexant, CX28344 Datasheet - Page 145

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Value after reset: 00(h)
Direction: Read only
Value after enable: 00(h)
EXZCtrltr
XdgrCtrltr
LCVCtrltr
FEBECtrltr
PthCtrltr
FerrCtrltr
PdgrCtrltr
28348-DSH-001-B
EXZCtrltr
7
XdgrCtrltr
Excessive Zeros Counter Interrupt—Set high on EXZ error counter roll over or saturation. The
EXZ Counter Interrupt Enable bit, EXZCtrlE bit in Counter Interrupt Control register,
determines the status of the counter (rollover or saturation).
X-Bits Disagreement Counter Interrupt—Set high if the X-Disagreement counter has either
rolled over or is saturated. The X Disagreement Counter Interrupt Enable bit (XDgrCtrIE)
determines the status of the counter (roll-over or saturation). In E3-G.751 and E3-G.832
modes, this bit is low because there are no X-bits.
LCV Counter Interrupt—Set high on an LCV error counter rollover or saturation. The LCV
Counter Interrupt Enable bit (LCVCtrIE) determines the status of the counter (roll over or
saturation).
FEBE Event Counter Interrupt—Set high if the FEBE event counter has either rolled over or is
saturated. The FEBE Event Counter Interrupt Enable bit determines the status of the counter
(roll-over or saturation).
In E3-G.751 and DS3-M13/M23 modes, this bit is low because there is no FEBE/REI event
defined.
Path Parity Error Counter Interrupt—In DS3 mode, set high if the Path Parity Error counter
has either rolled over or is saturated. The Path Parity Error Counter Interrupt Enable bit
determines the status of the counter (roll-over or saturation).
In DS3-M13/M23, E3-G.751, and E3-G.832 modes, this bit is low because there is no path
parity check.
Frame Error Counter Interrupt—Set high when the frame error counter has either rolled over
or is saturated. The Frame Error Counter Interrupt Enable determines the status of the counter
(roll-over or saturation).
P-Bits Disagreement Counter Interrupt—Set high if the P disagreement counter has either
rolled over or is saturated. The Disagreement Counter Interrupt Enable bit determines the
status of the counter (roll over or saturation). In E3-G.751 and E3-G832 modes, this bit is low
because there is no parity disagreement event defined.
6
Counter Interrupt Status Register (SR02i)
The Counter Interrupt Status register contains status information about active
interrupts needing service from the controller. This register needs to be read by the
controller upon receiving a counter interrupt to determine the source of the interrupt.
The interrupt indications are active high in the register and are available even if they
are not enabled to be visible on the INTR* output pin. Servicing clears this interrupt
indication as described in
The bits in this register are cleared when the register is read.
LCVCtrltr
5
Mindspeed Technologies™
FEBECtrltr
4
Section
PthCtrltr
2.3. Counter operation is discussed in
3
FerrCtrltr
2
PdgrCtrltr
1
Section
ParCtrltr
0
Registers
3.3.
3
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33