CX28344 Conexant, CX28344 Datasheet - Page 129

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Default after rest: 00(h)
Direction: Read/Write
Modification: Bits 4–6: dynamic; Bits 0–3, 7: static
RxAutoAll1
RefrmStp
RxAIS
RxAll1
RxOvhMrk
RxFIFEn
28348-DSH-001-B
RxAutoAll1
7
RefrmStp
Receive Automatic All 1s—Set to enable automatic generation of an all-1s stream on RXDAT
pin in response to a fault detection. When set and a LOS, OOF, AIS, or Idle are detected in
DS3 mode or LOS, OOF, or AIS are detected in E3 mode, the data received on RXPOS,
RXNEG is presented to the receiver circuit, but is not present on RXDAT pin. It is overwritten
by an all 1s stream. The assertion of all 1s continues as long as one or more of these conditions
is valid. When clear, all 1s sequence on RXDAT pin occurs due to RxAll1 bit in this register.
RxAll1 and RxAIS bits have precedence over the RxAutoAll1 bit.
Reframe Mechanism Stop—This bit controls the behavior of the frame-search mechanism.
When this bit is set, no frame-search is conducted (regardless of OOF status) when it has been
cleared frame-search resumes shifted forward by one bit from the current frame position, until
a new framing is located when it is cleared searching occurs in response to an OOF status.
Receive Data Stream AIS—Set to enable driving of an AIS pattern (in all DS3 and E3 modes)
on RXDAT pin. When set, data received on RXPOS, RXNEG is presented to the receiver
circuit but is not present on RXDAT pin. Detection and the count of errors, alarms, and events
continue while this mode operates. When cleared, data received on RXPOS, RXNEG, and
processed by the receiver circuit is present on RXDAT pin. If both RxAll1 and RxAIS are
active, a data stream of all 1s is generated.
Receive Data Stream is All 1s—Set to enable driving an all-1s stream on RXDAT pin. When
set, data received on RXPOS, RXNEG is presented to the receiver circuit, but is not present on
RXDAT pin. Detection and the count of errors, alarms, and events continue while this mode
operates. When cleared, the data received on RXPOS, RXNEG, and processed by the receiver
circuit is present on RXDAT pin. If both RxAll1 and RxAIS are active, data stream of all 1s is
generated.
Receive Overhead Bits Mark—This bit controls behavior of the RXMSY pin. When set,
RXMSY marks the bit positions of all overhead bits. When cleared, RXMSY marks the
beginning of a new frame. (See
Receiver FIFO Enable—Set to enable usage of the receiver FIFO buffer to provide jitter
elasticity to the input data stream. When set, data from the B3ZS/HDB3 decoder is sampled
into the FIFO buffer using LINECK clock, and is taken out of the FIFO buffer according to
RXCKI clock. When cleared, the FIFO buffer is bypassed, data goes from the decoder directly
into the frame recovery circuit and the only clock used in the receiver circuitry is LINECK.
Activation or deactivation of the FIFO buffer causes internal circuits to switch between clocks
after writing to this bit. The microprocessor should not access any of the device registers (read
or write) for 20 slowest clock cycles.
6
Feature5 Control Register (CR08i)
NOTE:
RxAIS
5
Mindspeed Technologies™
To produce a forced reframe, the microprocessor usually needs two write cycles, the
first to write 1 to the bit, and then to write 0 to it.
RXAll1
4
Section
2.2.2).
RxOvhMrk
3
RxFIFEn
2
RxInvClk
1
LRxCkRis
0
Registers
3
-
17