CX28344 Conexant, CX28344 Datasheet - Page 104

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.3
2.3.1
2.3.2
2.3.3
2-58
Microprocessor Interface
Address/Data Bus
Control Signals
Interrupt Requests
The Microprocessor Interface (MPU), provides the capability of configuring the
CX28342/3/4/6/8, reading status registers and counters, and responding to interrupts.
The interface supports Intel 8051, 8151, 8251 and Motorola 68000, 68020, 68030
processors. The Motorola mode is a SRAM like interface. EBUS is also supported for
Intel type glueless, and for Motorola types with external address latching. In the Intel
mode, the address and data are multiplexed, while in the Motorola mode, the address
and data are separate pins. Only asynchronous read and write mode is supported. The
asynchronous mode runs internally at channel 1 transmitter clock frequency.
The microprocessor interface is made up of the following pins: MOTO*, CS*, ALE,
DS*/RD*, R/W*/WR*, DTACK*, AD[7:0], A[8:0], INTR*, RESET*. A detailed
description of the MPU pins is provided in the pin list table.
In the Non-Multiplexed Address Mode, A[8:0] provides the address for register
access. In the Multiplexed Address Mode, A[8] and AD[7:0] provides the address. In
both modes, data bytes flow over the shared bidirectional, byte-wide bus, AD[7:0].
Four signals control the operation of the interface port: ALE, CS*, DS*/RD*, and R/
W*(WR*). An additional pin, MOTO*, selects whether the interface signals are a
Motorola or Intel type.
When MOTO* is low, indicating a Motorola-style interface, CS*, R/W*, and DS*
signals are expected. When MOTO* is high, indicating an Intel-style interface, CS*,
ALE, RD*, and WR* signals are expected.
When MOTO* is high, address lines are multiplexed with data. This pin is tied high
for Intel devices and tied low for Motorola devices.
The INTR* output pin is an active-low, open-drain type output, that provides a
common interrupt request for all four channels.
Each channel includes interrupt status registers and interrupt enable registers or
interrupt enable bits combined in control registers. Events, such as alarm status
changes, latch in status registers until read by the microprocessor or until another
action is taken. Most of the status bits have a corresponding interrupt enable bit to
enable or disable interrupt generation. If the specific interrupt is enabled and
interrupts from this channel are enabled, INTR* goes low or active.
Status bits from each channel are gated with the corresponding enable bits in the
control registers. They go to the Source Channel Status register providing information
NOTE:
Mindspeed Technologies™
Accessing or using the additional framers and the associated registers within
CX28346 and CX28348 requires the use of additional pins as outlined in
and
Tables 1-9
and 1-10.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
Chapter 1