CX28344 Conexant, CX28344 Datasheet - Page 106

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.3.6
2-60
Initialization Guidelines
The following device status is true after reset:
The order of programming does not matter as long as the Chnl(i)E (Channel Enable)
bits and Chnl(i)IE (Channel Interrupt Enable) in the General Control register are kept
low, i.e., the channels are disabled and the interrupts are globally masked. After the
desired modes, features, interrupt masks, overhead control bits, and data link channels
are set and enabled, the General1 Control register should be written to enable the
desired channels and interrupts.
When a channel is enabled after reset, and if TXSYIn is set, the transmitter waits for
the first synchronization pulse to start functioning. Until this pulse is sensed, the
transmitter system side signals are inactive, i.e., TXGAPCK and TEXTCK are low or
high (according to TxInvClk bit), and data is not sampled from TXDATI and TEXT
pins. TXPOS and TXNEG on the line side are also held low until the first
synchronization pulse is generated.
If TXSYOut is set, the transmitter starts working immediately after the channel is
enabled; it generates a synchronization pulse and drives the clocks and signals as
programmed.
The receiver system interface starts to work immediately after enabling the channel.
When enabled after reset, the receiver starts in an out-of-frame state. It starts an
internal frame counting and searches for framing pattern alignment in the received
data stream. The system side signals of the receiver start functioning immediately.
Disabling of a channel is done by clearing its Chnl(i)E bit in the General1 Control
register. When a channel is disabled after being operational, the control registers are
unaffected, and the status bits and counters maintain their value (to enable
NOTE:
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All the channels are disabled.
The control registers, status registers, and the counters are at their default values.
The default mode after reset is DS3-M13/M23.
All the interrupts are disabled.
FEAC channel and the data link FIFOs are disabled.
The Overhead bits are programmed to be generated internally.
The system side pins are inactive and have a value according to their control bits
default configuration (TXGAPCK, TEXTCK, RXGAPCK, REXTCK, and
RXMSY are zero; RXDAT is undefined; TXSY is High Z until configured.
VCO output is active all the time.
On the line side, TCLKO is active and reflects TXCKI. TXPOS and TXNEG are
forced to zero.
Mindspeed Technologies™
Before enabling the channels to be operational, the control registers should be
programmed to the desired operating mode. TXSY direction must be set to enable
correct operation of the transmitter.
Some of the control registers can be changed dynamically, i.e., while the channel is
enabled and working (interrupt’s mask or message byte, for example). Some of the
control registers are limited to be changed only when the channel is disabled (frame
format, for example).
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B