CX28344 Conexant, CX28344 Datasheet - Page 132

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Table 3-4. E3-G.832 Mode Field Interpretation
AutoRAI
ExtFEBE/Cj
3-20
DLMod[2]
0
0
0
0
1
1
1
1
Automatic RAI/RDI Generation Control—Set to enable automatic generation of the RAI or
RDI alarm in response to a fault detection. When set, an automatic assertion of the RAI bit in
E3-G.751 mode or RDI bit in E3-G.832 mode occurs once the receiver detects a LOS or OOF
condition. The automatic assertion continues as long as one or more of these conditions is
valid. The TxAlm [1] bit in the Mode Control register still effects RAI/RDI generation in E3
mode while this bit is set. When clear, RAI and RDI generation occurs due to the TxAlm [1]
bit in the Mode Control register and there is no automatic generation. This bit has no effect in
DS3 mode. Generation of an RAI alarm in DS3 mode is controlled only by TxAlm bits.
External FEBE/Justification Control— Set to enable insertion of FEBE or Justification
Control bits via the TEXT pin. In DS3-C Bit Parity mode, setting this bit enables insertion of
FEBE field via TEXT pin. In DS3-M13/M23 mode, setting this bit enables insertion of all C-
bits (used for Justification Control) via TEXT pin. In E3-G.751 mode, setting this bit enables
insertion of all Cj bits (used for Justification Control) via TEXT pin. In E3-G.832 mode,
setting this bit enables insertion of REI bit in MA byte via TEXT pin. When this bit is cleared,
FEBE bits are transmitted automatically upon detection of framing or CP error by the receiver
according to the contents of FEBEC/PT field described in the Feature1 Control register, DS3-
C Bit Parity mode. In DS3-M13/M23 mode or E3-G.751 mode, Justification Control bits are
inserted via the data stream when this bit is cleared. In E3-G.832 mode, the REI bit is set
automatically by the transmitter upon detection of BIP-8 error if this bit is cleared.
DLMod[1]
0
0
1
1
0
0
1
1
DS3-C Bit Parity
DLMod [0] controls the reserved C-bits (C12, Cb2, Cb6, and Cb7) generation. When
set, these bits are inserted via the TEXT pin. When cleared, these bits are
automatically generated as all 1s. In this mode, the bit is static.
DLMod[0]
0
1
0
1
0
1
0
1
Mindspeed Technologies™
Data link on the NR byte is disabled and the chip automatically generates an
FF(h) pattern on these bits. Data link on the GC byte is disabled and the chip
automatically generates an FF(h) pattern on these bits.
Data link on the NR byte is disabled, and the chip automatically generates an
FF(h) pattern on these bits. GC data is inserted via the TEXT pin and is
unaffected by the internal HDLC circuit.
Data link on the NR byte is disabled and the chip automatically generates an
FF(h) pattern on these bits. GC data is inserted through the Transmit Data Link
FIFO buffer and is processed by the internal HDLC circuit.
NR data is inserted via the TEXT pin, it is unaffected by the internal HDLC
circuit. Data link on GC byte is disabled and the chip automatically generates
FF(h) pattern on these bits.
NR data is inserted via the TEXT pin; it is unaffected by the internal HDLC
circuit. GC data is inserted through the Transmit Data Link FIFO buffer and is
processed by the internal HDLC circuit.
NR data is inserted through the Transmit Data Link FIFO buffer and is
processed by the internal HDLC circuit. GC data is inserted via the TEXT pin
and is unaffected by the internal HDLC circuit.
NR data is inserted through the Transmit Data Link FIFO buffer and is
processed by the internal HDLC circuit. Data link on GC byte is disabled and the
chip automatically generates an FF(h) pattern on these bits.
Both NR and GC data are inserted via the TEXT pin; they are unaffected by the
internal HDLC circuit.
Description
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B