CX28344 Conexant, CX28344 Datasheet - Page 70

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.1.3.2
2-24
FIFO Control Circuitry
The transmit data link side (TDL) of each framer includes a 128-byte FIFO buffer that
is additional to a 128-byte receiver side data link FIFO buffer (RDL). The FIFO
buffer is filled by the microprocessor with the data bytes to be transmitted for each
message and also provides interrupts and status bits to indicate its condition.
Writing to the FIFO
The FIFO buffer is written using the microprocessor interface. Writing a byte each
time to the Transmit Data Link Message Byte register (TxDLMsg [7:0] byte) fills the
FIFO buffer with a new message. The writing of the message byte adds it to the FIFO
buffer.
The Transmit Data Link Message Byte register has two addresses. The low address
should be used to write all message bytes except the last byte of the message. The
high address is used to write the last byte of the message. The writing to the high
address marks the written byte as the end of message byte (EOM). The next byte that
is written to the FIFO buffer belongs to a new message.
TDL FIFO Related Interrupts
All TDL FIFO interrupts are maskable individually. Settings in the Transmit Data
Link Control register control the enabling and disabling of the interrupts.
The TDL FIFO provides the following interrupts:
!
!
!
TDL FIFO Near-Empty—(interrupt enabled by setting TxNEIE bit to 1)
" Turned on when the number of data bytes that remains to be transmitted in the
" Turned off when the number of data bytes that remained to be transmitted in
TDL FIFO underrun—(interrupt enabled by setting TxURIE bit to 1)
" Turned on when the FIFO buffer is empty, if the last message byte that was
" Turned off when the Transmit Data Link FEAC Status register is read.
TDL message transmitted —(interrupt enabled by setting TxMsgIE bit to 1)
" Turned on when the last bit of the closing FLAG of a message is transmitted.
" Turned off when the TxMsg status bit at the Transmit Data Link FEAC Status
FIFO buffer becomes equal to or falls below the programmable Near-Empty
threshold level and the Near-Empty indication is not set.
the FIFO buffer becomes higher than the programmable Near-Empty threshold
level.
The range of Near-Empty threshold settings is 0 to 126, and is set in
TxNEThr[6:0] at the Transmit Data Link Threshold Control register.
Setting Near-Empty threshold to NE = 0 to 126, means that Near-Empty event
is declared when the number of data bytes remaining in the FIFO buffer is
equal or less than NE.
transmitted did not indicate an end of message byte, and the inner HDLC
circuitry requests the FIFO buffer for another byte to transmit.
register is read.
Mindspeed Technologies™
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B