CX28344 Conexant, CX28344 Datasheet - Page 73

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.3.5
28348-DSH-001-B
FIFO Special Events
End of Message Event
The system indicates End of Message (EOM) by writing the last byte of the message
to the high address of the Transmit Data Link Message Byte register. When the TDL
circuitry encounters the EOM indication set for a byte in the FIFO buffer, and after
transmitting the last byte, it checks whether FCS sequence sending is set (bit
TxFCSEn is set to 1 in Transmit Data Link Control register). If set, FCS bytes are
sent, followed by at least two FLAG sequences before starting transition of the next
message in the FIFO buffer (if there is one).
If the EOM byte is the last byte in the FIFO buffer, the TDL circuitry continues
transmitting FLAG sequences (after transmitting the last byte and FCS, if enabled)
until a new message byte is written to the FIFO buffer.
Near-Empty Event
The Near-Empty event is declared when the number of bytes remaining in the TDL
FIFO buffer is less than or equal to the number programmed at the Near-Empty
threshold the value of which can be set to 0 to 126. The Near-Empty event results in
an interrupt, if enabled. It is used to help the system to control and use the FIFO buffer
FIFO Underrun
A FIFO underrun condition is caused when the internal transmit logic has emptied the
FIFO buffer without encountering an end of message and the transmit logic request
for the next byte to be transmitted. This causes an Abort sequence (16 consecutive 1s)
to be transmitted followed by at least two FLAG sequences. After an ABORT + two
FLAG sequences, the transmit internal circuitry is ready to start transmitting a new
message as soon as it is written to the FIFO buffer and writing to the FIFO buffer is
allowed.
As soon as an underrun condition is declared internally, an interrupt is issued (if
enabled) and the FIFO buffer prevents additional data bytes to be written to it. The
underrun interrupt is cleared upon reading the Transmit Data Link FEAC Status
register. Writing to the FIFO buffer is enabled again only after the interrupt is cleared.
The system checks the amount of data bytes that may have been written and lost
between the time the first underrun interrupt occurred and the system reads the FIFO
status register and senses a underrun condition.
Writing to FIFO when FIFO is Full
When the FIFO buffer is FULL, writing to the FIFO buffer by the microprocessor is
ignored by the circuit, and no indication for ignoring written data during FIFO Full
condition is supplied. Neither data bytes and pointers of the FIFO buffer, nor the
HDLC formatting and message providing mechanisms are not affected by writing into
the FIFO during FIFO FULL condition.
Mindspeed Technologies™
Functional Description
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