CX28344 Conexant, CX28344 Datasheet - Page 124

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Default after reset: 00(h)
Direction: Read/Write
Modification: Dynamic
LOSEndIE
IdleEndIE
YelEndIE
AISEndIE
OOFEndIE
3-12
Reserved
7
Reserved
start, the interrupt is asserted and OOFStrt bit in Alarm Start Interrupt Status register is set.
When this bit is cleared, detection of OOF start sets the appropriate status bit; however, an
interrupt is not activated.
Loss of Signal End Interrupt Enable—Set to enable interrupts to be asserted on INTR* pin due
to detection of LOS condition end in all modes. When a LOS condition end is detected, the
interrupt is asserted and LOSEnd bit in Alarm End Interrupt Status register is set. When this
bit is cleared, detection of LOS end sets the appropriate status bit; however, an interrupt is not
activated.
Idle Interrupt End Enable—Set to enable interrupts be asserted on INTR* pin due to detection
of Idle event end in DS3 mode. When the receiver detects an Idle end, the interrupt is asserted
and IdleEnd bit in Alarm End Interrupt Status register is set. When this bit is cleared, detection
of Idle end sets the appropriate status bit; however, an interrupt is not activated. This bit has no
effect in E3-G.751 and E3-G.832 modes.
Yellow Alarm End Interrupt Enable—Set to enable interrupts to be asserted on INTR* pin due
to detection of RAI/RDI event end in all modes. When the receiver detects an RAI/RDI event
end, the interrupt is asserted and YelEnd bit in Alarm End Interrupt Status register is set. When
this bit is cleared, detection of RAI/RDI end sets the appropriate status bit; however, an
interrupt is not activated.
Alarm Indication Signal End Interrupt Enable—Set to enable interrupts to be asserted on
INTR* pin due to detection of AIS event end in all modes. When the receiver detects an AIS
event end, the interrupt is asserted and AISEnd bit in Alarm End Interrupt Status register is set.
When this bit is cleared, detection of AIS end sets the appropriate status bit; however, an
interrupt is not activated.
Out of Frame End Interrupt Enable—Set to enable interrupts be asserted on INTR* pin due to
detection of OOF condition end in all modes. When the receiver detects an OOF condition
end, the interrupt is asserted and OOFEnd bit in Alarm End Interrupt Status register is set.
When this bit is cleared, detection of OOF end sets the appropriate status bit; however, an
interrupt is not activated.
6
Alarm End Interrupt Control Register (CR03i)
NOTE:
Reserved
5
Reserved bits in Control registers must be set to zero.
Mindspeed Technologies™
LOSEndIE
4
IdleEndIE
3
YelEndIE
2
AISEndIE
CX28342/3/4/6/8 Data Sheet
1
28348-DSH-001-B
OOFEndIE
0