CX28344 Conexant, CX28344 Datasheet - Page 55

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Figure 2-9. E3-G751 Mode where TXSY is an Input Signal
Figure 2-10. E3-G.832 Mode where TXSY is an Output Signal Indicating Frame Start Sync
28348-DSH-001-B
TXGAPCK(inv)
TXGAPCK
TXGAPCK(inv)
TXDATI
TXCKI
TXGAPCK
TXSY
TXDATI
TXCKI
TXSY
In
last bit of E3-G.751 frame to the first bit of the next frame. In this case, the system can
return TXSY to low after at least one TXCKI clock.
Transmit Operation in E3-G.832 Mode
In the E3-G.832 mode of operation, TXCKI pin is connected to a 34.368 MHz clock.
When the TXSY signal is provided externally, it should have a low-to-high transition
from the last bit of the E3-G.832 frame to the first bit of the framing alignment octet
of the next frame.
When provided internally and used as a frame start synchronization signal, it has a
low-to-high transition at the same position. TXSY output returns to low after the last
bit of GC field.
If the TXCKI pin is used as an overhead indication output signal, TXSY is low during
all Overhead bits positions (i.e., low during FA1, FA2, EM, TR, MA, NR, and GC
bytes) and high during data bits position regardless of Overhead bits source.
In
synchronization.
GC (8 bits)
Figure
Figure
Payload
2-9, the TXSY signal is an input having a low-to-high transition from the
2-10, the TXSY pin is an output signal indicating frame start
1888 Payload
Mindspeed Technologies™
bits
Low during 16 bits
10 FAS bits
FA1 + FA2
16 bits
A bit
N bit
464 Payload
High during 2408 bits
bits
372 Payload
bits
Low during 8 bits
C11
EM (8 bits)
C12
C13
Payload
Functional Description
100542_012
100542_013
2
-
9