CX28344 Conexant, CX28344 Datasheet - Page 133

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
ExtCP/TR
ExtFEAC/PD
ExtDat
Default after reset: 00(h)
Direction: Read/Write
Modification: Static
ExtStf
ExtFrmAl
ExtP
ExtRAI
28348-DSH-001-B
Reserved
7
Reserved
External CP/Trail Trace Control—Set to enable insertion of CP-bits or TR byte via TEXT pin.
In DS3-C Bit Parity mode, setting this bit enables insertion of CP field via TEXT pin. In E3-
G.832 mode, setting this bit enables insertion of Trail Trace byte via TEXT pin. In E3-G.832,
when this bit is cleared, the transmitter automatically transmits 00(h) on TR byte. In DS3-
M13/M23 and E3-G.751 modes, this bit has no effect.
External FEAC/Payload Dependent/Multiframe Indicator Field Control—Set to enable
insertion of FEAC channel or payload dependent field via TEXT pin. In DS3-C Bit Parity
mode, setting this bit enables insertion of FEAC channel via TEXT pin. In E3-G.832 mode,
setting this bit enables insertion of payload dependent, multiframe indicator field in MA byte
via TEXT pin. When this bit is cleared, FEAC channel is inserted through a programmable
register (Transmit FEAC Channel Byte) in DS3-C Bit Parity mode. In E3-G.832, payload
dependent field is inserted through a programmable register (MAPD field in Feature4 control
register) when this bit is cleared and SSMEn bit (in Feature4 Control register) is also cleared.
If SSMEn is set, i.e., bits 6–7 in MA byte are used as a multiframe indicator, the MI is
internally produced cycling through the values 00, 01, 10, and 11 on an arbitrarily-defined,
4-frame multiframe. In DS3-M13/M23 and E3-G.751 modes, this bit has no effect.
External Data Control—Set to enable all overhead bits to be inserted via the data stream.
When set, this bit overrides the rest of the control bits in this register. It disables internal
generation of overhead bits (automatic or through programmable registers) and forces the
device to use the overhead bits inserted in the data stream of the Transmit Overhead Insertion2
Control register. When clear, overhead configuration is determined by the rest of the control
bits as described above. This bit affects all modes. Setting of TxAlm [1:0] bits is effective even
during ExtDat = 1.
External Stuff Bits—Set to enable insertion of Stuff Opportunity bits via TEXT pin in DS3-
M13/M23 and E3-G.751 modes. When clear, stuff bits are inserted with the payload. This bit
has no affect in DS3-C-bit parity and E3-G.832 modes.
External Frame Alignment Bits—Set to enable insertion of F and M-bits (DS3 mode), FAS
(E3-G.751), FA1 and FA2 (E3-G.832) bits via TEXT pin. When clear, the frame alignment
bits are automatically generated by the internal circuitry.
External P-Bit Control—Set to enable insertion of P-bits via TEXT pin in DS3-C Bit Parity
and DS3-M13/M23 modes. When clear, P-bits are automatically calculated by the internal
circuitry. In E3-G.751 and E3-G.832 modes, this bit has no effect.
External X/A/RDI-Bit Control—Set to enable insertion of X-bits (in DS3), A-bit (in E3-
G.751), and RDI (in E3-G.832) via TEXT pin. It affects E3 when AutoRAI bit is clear.
6
Transmit Overhead Insertion2 Control Register (CR10i)
Reserved
5
Mindspeed Technologies™
Reserved
4
ExtStf
3
ExtFrmAl
2
ExtP
1
ExtRAI
0
Registers
3
-
21