CX28344 Conexant, CX28344 Datasheet - Page 115

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
3.2
28348-DSH-001-B
Register Address Map
Register addresses are 9 bits in length, A[8:0]. The two most significant bits, A[8:7],
represent the framer number, and the remaining seven bits, a[6:0], are the specific
register offset within the framer’s address space. With the CX28342/3/4 devices,
there is only one set of registers. For the CX28346/8, there are two sets of registers
with this addressing scheme, one associated with each chip select, CS[A]* and
CS[B]*.
Therefore, the same registers in different framers share the same offset. General
registers shared by framers use the lower offsets of each framer, but are only
implemented in Framer 1 address space. In the case of CS28346/8, the General
registers are implemented in Framers 1 and 5.
The address space of one channel is illustrated below:
For all devices, the base addresses are allocated as follows:
!
!
The addresses appearing in the following tables are offsets. The Addr column in the
following tables relates to the 7-bits offset address, A[6:0].
CX28342/3/4 or CX28346/8—CS[A] (Chip Select A)
" General registers—00 (b)
" Framer1—00(b)
" Framer2—01(b)
" Framer3—10(b)
" Framer4—11(b)
CX28346/8—CS[B] (Chip Select B)
" General Control registers—00(b)
" Framer5—00(b)
" Framer6—01(b)
" Framer7—10(b) [CX28348 only]
" Framer8—11(b) [CX28348 only]
00-01(h)
02-07(h)
08-09(h)
0A-0F(h)
10-13(h)
14-1F(h)
20-35(h)
36-3F(h)
40-52(h)
53-5F(h)
60-70(h)
71-7F(h)
Mindspeed Technologies™
General Control
Reserved
General Status
Reserved
General Counters
Reserved
Control Registers
Reserved
Status Registers
Reserved
Counters
Reserved
Registers
3
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3