CX28344 Conexant, CX28344 Datasheet - Page 126

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Default after rest: 01(h)
Direction: Read/Write
Modification: Bit 5: dynamic, bits 0-4: static
TxLOS
TxOvhMrk
TXSYOut
TXSYIn
TxInvClk
LTxCkRis
3-14
Reserved
7
Reserved
transmitted frame. In DS3-M13/M23 and E3-G.751 modes, this field has no effect.
Transmit Loss of Signal—This bit, when set results in the generation of all 0’s (LOS) on the
transmit line side. Setting this bit overrides any other programmed or inserted payload and
overhead pattern with 0s.
Transmit Overhead Bits Mark—This bit controls the behavior of TXSY pin when
programmed to be driven as an output. When set, TXSY marks the bit positions of all
overhead bits. When cleared, TXSY marks the beginning of a new frame.
TXSY Pin Output Control—This bit determines if TXSY pin is an output of the chip. When
set, this pin is an output, i.e., the transmitter circuit generates its own frame synchronization
mechanism and signals the frame start or the overhead bit positions (according to TxOvhMrk
bit) on TXSY pin to the system. When cleared, TXSY can be an input or undefined according
to the value of TXSYIn bit in this register. During and after reset, TXSY drives high Z, and is
neither in output state nor in input state.
TXSY in Input Control—This bit determines if TXSY pin is an input of the chip. When set,
this pin is an input, i.e., the system generates a synchronization pulse and the transmitter
circuit acts according to it. When cleared, TXSY can be an output or undefined according to
the value of TXSYOut bit in this register. During and after reset, TXSY drives high Z, and is
neither in output state nor in input state.
Transmit System Side Inverted Clocks—This bit controls the polarity of TXGAPCK and
TEXTCK output clocks. When the bit is cleared, TXGAPCK and TEXTCK rising edges are
derived from TXCKI falling edge. In this mode, both clock gaps are active low. When this bit
is set, TXGAPCK and TEXTCK are inverted, hence TXGAPCK and TEXTCK falling edges
are derived from TXCKI falling edge. In this mode, both clock gaps are active high.
LIU Transmit Clock Polarity Control—Used to define the TCLKO edge upon which the
transmitter output data (on TXPOS, TXNEG pins) is sampled by the LIU. When set, the data
is clocked out by the chip on the falling edge of TCLKO. It is sampled by the LIU on the rising
edge of TCLKO. When cleared, the data is clocked out by the chip on the rising edge of
TCLKO; therefore, it is sampled by the LIU on the falling edge of TCLKO.
6
Feature2 Control Register (CR05i)
NOTE:
NOTE:
TxLOS
5
Mindspeed Technologies™
TXSYOut and TXSYIn bits should not be set at the same time.
TXSYOut and TXSYIn bits should not be set at the same time.
TxOvhMrk
4
TXSYOut
3
TXSYIn
2
TxInvClk
CX28342/3/4/6/8 Data Sheet
1
28348-DSH-001-B
LtxCkRis
0