CX28344 Conexant, CX28344 Datasheet - Page 75

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.4
28348-DSH-001-B
FEAC Channel Transmission
A description of a FEAC channel is applicable to each framer on the device.
There are three sources available for transmission of FEAC bits in DS3 C-bit parity
mode that are set at the Transmit Overhead Insertion 1 Control register by bits ExtDat
and ExtFEAC/PD for each framer individually: from data, from an external pin, or
generated internally using the Transmit FEAC Channel Byte register and the
microprocessor. When TxFEAC bits source is from data (ExtDat = 1) or from an
external pin (ExtFEAC/PD = 1 and ExtDat = 0), no operation is done by the framer
except inserting TxFEAC bits to the transmitter data stream at the proper time (when
TxFEAC bits are inserted from an external pin). When TxFEAC is internally
generated (ExtFEAC/PD = 0 and ExtDat = 0), the code word to be transmitted at the
TxFEAC is taken from the Transmit FEAC Channel Byte register.
When TxFEAC is generated internally, the Transmit FEAC Channel Byte register
controls the byte to be transmitted on the TxFEAC channel. All messages transmitted
on this channel are in the form 0xxxmmm011111111. The right-most bit of this
sequence is the first bit transmitted on the channel. Only the 0xxxmmm0 byte of the
16-bit message is written to the Transmit FEAC Channel Byte register; the eight
consecutive 1s of the FEAC message are transmitted automatically.
The transmitter FEAC mechanism provides the microprocessor with an interrupt and
a status bit indicating that the interrupt’s source is the TxFEAC (transmit FEAC
channel Interrupt bit [TxFEACltr] at the Transmit Data Link FEAC Status register).
The setting of bit TxFEACIE at the Feature3 Control register can mask the interrupt.
The transmitter FEAC interrupt indicates that the last message was sent and a new
message byte can be written to the Transmit FEAC Channel Byte register.
A reset or returning to enable after a disable clears the TxFEAC interrupt (if it was
issued). A new interrupt is not issued until a new FEAC message is written and sent,
and until then, repetitive 1s are sent.
Activating transmission of AIS in C-bit parity mode in the middle of a FEAC message
transmission terminates the FEAC message. The FEAC state machine returns to IDLE
state, and no transmitter FEAC interrupt is issued. When AIS transmission is
deactivated, the transmitter sends IDLE sequence (repetitive 1s) on the FEAC channel
until a new message byte is written to Transmit FEAC Channel Byte register controls.
Transmission of yellow alarm or DS3 IDLE code in C-bit parity mode has no effect
on TxFEAC channel transmission.
Two modes of transmitting a FEAC message available using the Transmit FEAC
Channel Byte register are the Single code-word mode and the repetitive code-word
mode. These are set by bit FEACSin in the Feature3 Control register.
Mindspeed Technologies™
Functional Description
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