CX28344 Conexant, CX28344 Datasheet - Page 50

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
Figure 2-3. Tx System Side External Overhead Insertion (DS3 FEBE-only example)
2-4
TEXTCK(inv)
TEXTCK
TXDATI
TXCKI
TEXT
TXSY
Frame synchronization indicator. Functions either as input or an output pin.
When used as an input pin (TXSYIn is set to 1), it provides the external circuitry with
the ability to control frame start synchronization. It is sampled with the falling edge of
the TXCKI input clock. After the first TXSY input signal is provided, the transmitter
circuitry maintains the last synchronization until the next sync signal is provided on
TXSY. Thus, the system has the option of not providing any more sync pulses on
TXSY input as long as the old synchronization is valid.
The device resynchronizes within one frame time. When set as input, the transmitter
expects at least one TXSY input signal. Until the first TXSY input signal is supplied,
the framer is not synchronized and does not provide internal synchronization. In this
case, TEXTCK and TXGAPCK outputs remain disabled (long gap) until the first
TXSY input is provided. When TXSY input is provided, it should have a low-to-high
transition from the last bit of the one frame to the first bit of the next frame. The
framer watches the transition of TXSY input; when sampled high after it was sampled
low, the framer expects the first bit of the new frame to be inserted at TXDATI at the
same time. After TXSY input transitioned from low to high, it can be set low again
after one or more TXCKI clock. The framer maintains synchronization from the last
time TXSY input was provided.
When used as an output pin (by setting bit TXSYOut to 1), it has two modes of
operation. Setting TxOvhMrk bit in the Feature 2 Control register controls these
modes. It can function as a frame start synchronization signal or as an overhead
indication signal. In both cases, it is sampled out with the rising edge of TXCKI clock.
NOTE:
Cb41
Setup+Hold
169 bits
Cb41
84 Data + F2 bit
Mindspeed Technologies™
If sync signal is provided at an expected place according to the last sync signal (e.g.,
low-to-high transition over X1-bit in DS3 mode), it does not affect the old
synchronization. If a sync signal is provided on TXSY pin not according to old
synchronization, new synchronization takes place and incorrect operation (mainly at
TXGAPCK and TEXCK) can occur near the sync signal.
+84 Data
Subframe 4 of Frame I
Cb42
Setup+Hold
169 bits
Cb42
84 Data + F3 bit
+84 Data
Cb43
Setup+Hold
4419 bits
Rest of Frame I +
Cb43
Part Frame I+1
Subframe 4 of Frame I+1
CX28342/3/4/6/8 Data Sheet
Setup+Hold
Cb41
Cb41
28348-DSH-001-B
100542_006