CX28344 Conexant, CX28344 Datasheet - Page 109

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.4.2
2.4.3
28348-DSH-001-B
Remote Line Loopback
Payload Loopback
The remote line loopback loops receive data after B3ZS/HDB3 decoding and before
frame recovery back to the line. If the receiver FIFO buffer is disabled, decoder
output is connected to transmitter B3ZS/HDB3 encoder input. If the receiver FIFO
buffer is enabled, the FIFO output is connected to transmitter B3ZS/HDB3 encoder
input. The remote line loopback provides some LCV error correction due to the path
through the decoder and the encoder. Activation of this loopback does not affect the
receiver data path. The received data is still present on RXDAT pin (it can be replaced
by an all-1s or AIS stream by programming RxAll1 or RxAIS bits in Feature5 Control
register). Error insertion on the looped frame is not valid.
The whole transmitter circuit works with the receiver clock (either LINECK or
RXCKI). System interface clock outputs (TXGAPCK and TEXTCK) cannot be
related to TXCKI in this mode and are inactive. TXSY is also inactive. If TXSY is
programmed as an input, it is ignored by the transmitter. If TXSY is programmed as
an output, it is blocked by the transmitter.
Overwriting the looped frame by an AIS pattern and transmission of AIS to the line is
enabled by programming TxAlm bits in Mode Control register. However, the
generated pattern is not aligned to the looped frame boundaries and is initiated and
terminated once TxAlm bits change. Idle pattern and RAI transmission due to TxAlm
bits are not enabled during this loopback.
When TxLos bit in Feature2 Control register is set, an all-0s signal is output to the
transmitter and overrides the content of the frame looped from the receiver.
This loopback is activated by setting RlineLp bit in the Feature3 Control register.
The payload loopback loops the received frame from the frame recovery circuit
output through the transmitter frame generation circuit input back to the line. The
transmitter must be programmed through Transmit Overhead Insertion1&2 registers
to an internal generation of the Overhead bits, i.e., nothing is inserted via TXDATI or
TEXT pins. The only exception is that justification control and Stuff Opportunity bits
should be selected to be driven with the data stream, enabling the transmitter to
receive them from the receiver with the payload. The entire transmitter circuit works
with the receiver clock (either LINECK or RXCKI). The system interface clock
outputs (TXGAPCK and TEXTCK) cannot be related to TXCKI in this mode and are
inactive. The transmitter circuit gets the frame alignment signal from the receiver with
the data that is looped. TXSY is inactive; if TXSY is programmed as an input, it is
ignored by the transmitter. If TXSY is programmed as an output, it is blocked by the
transmitter.
The payload loopback provides framing bits and some LCV error correction due to
the path through the decoder, frame recovery, frame generation, and encoder.
Activation of this loopback does not affect the receiver data path. The received data is
present on RXDAT pin (it can be replaced by an all-1s or AIS stream by
programming RxAll1 or RxAIS bits in Feature5 Control register). Error insertion on
the looped frame is valid in this mode. Overwriting the looped frame by an AIS
pattern and transmission of AIS to the line is enabled by programming TxAlm bits in
Mode Control register. The generated pattern is aligned to the looped frame
boundaries, and initiated and terminated similarly to normal operation (i.e., when not
Mindspeed Technologies™
Functional Description
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