CX28344 Conexant, CX28344 Datasheet - Page 154

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
3.6
Value after reset: 00(h)
Direction: Read/Write
Value after enable: 0000(h)
ParCtr[15:0]
3-42
ParCtr[15]
ParCtr[7]
15
7
ParCtr[14]
ParCtr[6]
Parity Error Counter—In DS3 mode, increments for each M-frame where the calculated parity
of the received data bits of the previous M-frame does not match the received parity bits. If the
two parity bits are different, this counter increments. In E3-G.832 mode, it increments for each
frame where the calculated BIP-8 pattern of the received data bits of the previous frame do not
match the received EM byte. The counter increments are per byte, not bits. In E3-G.751 mode,
this counter is not used.
Counters
14
6
There are eight error counters for DS3/E3 errors. All are 16-bit counters except the
LCV counter, which is 24 bits long. If the interrupt for a particular counter is not
enabled, the counter saturates at 65,535 (LCV = 16,777,215). When more than 65,535
(LCV = 16,777,215) counts of that error are received, the saturation indication
appears in the Counter Interrupt Status register. The saturation indication is cleared
when the Counter Interrupt Status register is read. The counter is cleared when the
counter is read.
If the interrupt for a particular counter is enabled in the Interrupt Control register, the
counter does not saturate but rolls over and continue counting from zero. An interrupt
is generated on the INTR* pin and appears in the Counter Interrupt Status register
when the counter rolls over to a count of zero. The interrupt is cleared when the
Counter Interrupt Status register is read. The counter is cleared when the counter is
read. The counters count according to indications set by the receiver circuit. For
details, see
All counters are cleared when read by the microprocessor. The interrupt indication for
a particular counter is cleared when the Counter Interrupt Status register is read.
Software should read the low byte first and then the high byte to prevent any missed
counts. All counters are designed so that errors occurring during reads by the
microprocessor are not be missed or double-counted.
The OneSec timer is a special counter that does not belong to the family of error and
event counters. The microprocessor does not read the general counter because its only
function is to count one-second intervals and then roll over and set a status/interrupt.
The effect of this counter is fully described in
NOTE:All counters must be in the saturating mode for this mode to function properly.
DS3/E3 Parity Error Counter (Ctr00i)
ParCtr[13]
ParCtr[5]
13
5
Section
Mindspeed Technologies™
ParCtr[12]
ParCtr[4]
2.2.5.
12
4
ParCtr[11]
ParCtr[3]
11
3
Section
ParCtr[10]
ParCtr[2]
10
2
2.2.6.
ParCtr[1]
ParCtr[9]
CX28342/3/4/6/8 Data Sheet
1
9
28348-DSH-001-B
ParCtr[0]
ParCtr[8]
0
8