CX28344 Conexant, CX28344 Datasheet - Page 90

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.2.5
2-44
Performance Monitoring
Performance monitoring function is available through event indicators, counters, and
interrupts. An event indicator represents an event, such as parity error, or a change of
status, such as out-of-frame. These event indicators can be the cause for an interrupt
or the increment of a event counter. The event indicators are BPV, EXZ, LCV, FBE,
PER, PBD, PPER, XBD, FEBE/REI, LOS, OOF, SEF, AIS, IDLE, and RAI/RDI.
These event indicators are externally identifiable through interrupts, counters or the
status registers they affect. All the counters used to count the events are 16 bits long
except the LCV counter, which is 24 bits long. If these counters are read once per
second, the size of the counters guarantees non-saturation in normal conditions
(assuming a BER of less than or equal to 1E3).
Depending on the settings of the Counter Interrupt Control register, the counters
function either in saturation mode or roll-over mode.
If the interrupt associated with a specific counter is masked, the counter operates in
the saturation mode. In this mode, the counter counts up to the highest possible value
and turns on a saturation indication bit in the Counter Interrupt Status register. The
counter and the indication bits are cleared when read.
If the interrupt associated with a specific counter is unmasked, the counter operates in
the roll-over mode. In this mode, the counter resumes counting from zero after
counting up to the highest value. An interrupt is generated, and an interrupt
identification bit is set in the Counter Interrupt Status register. The counter and the
status register are cleared when read.
When the INTR* pin is active, an appropriate interrupt identification bit is active or
set. Unless otherwise qualified, the interrupt is associated with the identification bit,
and both are cleared when the identification bit is read. The status indication bits often
parallel the interrupts and can be used for applications preferring polling to interrupts.
Once an interrupt occurs the microprocessor should read the SrcChnl1-SrcChnl4
fields of the Source Channel Status register to identify the interrupt originating
channel. Once the channel is identified then read the Interrupt Source Status register
to identify which sub-block initiated the interrupt. Finally read the interrupt
identification fields of the Status Indication register for that sub-block to identify the
type of interrupt. All interrupts are masked on reset. They are unmasked or made
active by setting the appropriate fields in the AlarmStartInterrupt and
AlarmEndInterrupt registers.
The following sections describe the various event indicators encountered in DS3/E3.
NOTE:
NOTE:
Mindspeed Technologies™
In reading 16-bit/24-bit counters, software should read the low byte first and then the
high byte/bytes. The counters do not miss or double count any errors during the
microprocessor reads. At reset all counters are cleared.
The presence of one event indicator does not inhibit the other events from occurring
nor inhibit the other data channels (Data Link or FEAC). For example, FBE is still
active in OOF, and internal datalink processing is still active in AIS.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B