CX28344 Conexant, CX28344 Datasheet - Page 107

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
debugging). Unless the Chnl(i)IE bits are cleared (hence, globally masking the
interrupts), interrupts that were asserted continue to be active. Therefore, the disabled
channel’s interrupts should be masked in parallel with disabling the channel (by
clearing Chnl(i)IE bit).
While a channel is disabled, the system side pins of the transmitter and receiver are
frozen in their last state and are inactive until the channel is enabled. RXGAPCK,
REXTCK, TXGAPCK, and TEXTCK can change their output polarity when the
channel is disabled if the corresponding Control bits are changed at that time. TXSY
also can change from output to input and vice versa if the Control bits are changed.
On the line side, TXPOS and TXNEG are forced to zero while the channel is disabled.
After disabling the channel, the desired modes and functions should be changed.
Then, the channel and its global interrupt mask should be enabled again. Some of the
status registers and the counters are affected by enabling the channel according to the
new mode set, or due to an old event’s end. The data link FIFO buffers are flushed.
The FEAC channel bytes are not relevant, and their operation starts as it would after
reset and enable. The transmitter and the receiver act as they would when enabled
after reset.
To enable programming of the control registers and reading of the counters and status
registers while the channel is disabled, the system (TXCKI) and line (LINECK and
optionally RXCKI) clocks must be supplied. The clocks can be disabled only when a
channel is completely shut down and is not going to be used.
Mindspeed Technologies™
Functional Description
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