CX28344 Conexant, CX28344 Datasheet - Page 113

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

3.1
28348-DSH-001-B
Register Address Map
3.0 Registers
The registers in this device are classified into three types: Control, Status, and
Counter registers. The Control registers configure the specific channels into their
desired working mode, enable or disable interrupts and miscellaneous features in the
devices. The Status registers report the occurrence of different events or triggers and
performance errors. If a Status register is combined with an interrupt that is enabled,
setting that Status registers to a logic 1 causes that interrupt to appear on the INTR*
pin.
Clearing that Status register deactivates that related interrupt. The Counters count
events and performance errors in the received signal and data path. The Counters are
combined with an interrupt, which if enabled, is asserted once a counter rolls over.
The Counters are cleared when the counters are individually read. A special additional
counter is the One-Second Timer (GCtr00), which is discussed in more detailed later
in the document.
The descriptions following this paragraph describe one register. Depending on the
device, the same group is multiplied (i) channel times and functions the same way for
every (i) channel. The General registers are the exception. With the CX28342/3/4
devices, there are only one set of general registers. For the CX28346/8, there are two
sets of general registers, one associated with each chip select, CS[A]* and CS[B]*.
These registers include the Source Channel Status, Part Number/Hardware Version,
and the One-Second Timer. The full address map for all channels can be found in
Section
Some Control registers can be modified, whether the channel is either disabled or
enabled or currently operating (dynamic modification). Some Control registers can
only be modified when the channel is disabled (static modification). Specifications
regarding each register are found in the following paragraphs. When a register with
mixed bits (both dynamic and static bits in the same register) is modified while
channel is enabled, the software must modify the dynamic bits, but leave the static
bits unchanged.
NOTE:
3.6.
Mindspeed Technologies™
The CX28346/8 devices have two interrupt pins, INTR[A]* and INTR[B]*
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