CX28344 Conexant, CX28344 Datasheet - Page 138

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Default after reset: 7F(h)
Direction: Read/Write
Modification: DL—static
RxNFThr [6:0]
Default after reset: FF(h)
Direction: Read/Write
Modification: Dynamic
TxFEAC[7:0]
3-26
TxFEAC[7]
Reserved
7
7
RxNFThr[6]
TxFEAC[6]
Receive Data Link FIFO Near Full Threshold—Set to the threshold value; used to indicate a
near-full FIFO event. The range of values available for this purpose is 2–127, where 02(h) is
interpreted as 2 and 7F(h) is interpreted as 127.
Transmit FEAC Channel Message Byte—If the mode is set to DS3-C Bit Parity, this register is
used as the data byte for the transmit FEAC channel transmitter. When this byte is in the form
0xxxxxx0 it is transmitted after every flag. If there is a 1 in either the most significant or least
significant bit of this register, an all-1s (idle) is transmitted on FEAC channel. An interrupt is
associated with this channel and is enabled by TxFEACIE bit in Feature3 Control register. For
interrupt activation, see
is transmitted last.
6
6
Receive Data Link Threshold Control Register (CR17i)
Transmit FEAC Channel Byte (CR18i)
Error Insertion Control Registers
Error insertion registers enable single insertion of different errors. Setting the relevant
bit causes insertion of the requested error at the next valid opportunity. The relevant
control bit clears once the error is inserted. Therefore, the control bits have to be
polled before setting them for the next error insertion. Several Error Insertion Control
bits can be set at the same time; each one of them is cleared when the appropriate
error is inserted.
NOTE:
RxNFThr[5]
TxFEAC[5]
5
5
Mindspeed Technologies™
The software can only set the Error Insertion bits. Writing 0 to these bits leaves them
unaffected. Some of the bits are valid only in certain modes. When not valid, setting
the bits has no effect and they are not cleared. Reserved bits are cleared to 0. Value
after enabling Error Insertion Control bits = 0.
Section
RxNFThr[4]
TxFEAC[4]
4
4
2.1.4. TxFEAC [0] bit is transmitted first and TxFEAC [7] bit
RxNFThr[3]
TxFEAC[3]
3
3
RxNFThr[2]
TxFEAC[2]
2
2
RxNFThr[1]
TxFEAC[1]
CX28342/3/4/6/8 Data Sheet
1
1
28348-DSH-001-B
RxNFThr[0]
TxFEAC[0]
0
0