CX28344 Conexant, CX28344 Datasheet - Page 60

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2-14
C-Bit Parity Mode Only: Overhead Insertion
In the C-bit parity mode of operation, the C-bits are divided into groups with the
following source options:
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AIC (Cb11)—Application Identification Channel. It is generated internally. The
transmitter inserts 1 to the transmitted data at the C11 place to indicate that the line
works with the C-bit parity application (a constant 1 at AIC-bit indicates C-bit
parity application).
FEAC (Cb13)—Far End Alarm Channel. When bit ExtFEAC/PD (Transmit
Overhead Insertion 1 Control register) is set to 1, Cb13 value is inserted through
the TEXT input pin. When bit ExtFEAC/PD is set to 0, Cb13 is internally
generated using the Transmit FEAC Channel Byte register and setting bit
FEACSin (single or repetitive mode bit) at the Feature3 Control register.
Path Parity (Cb3)—The three C-bits at subframe 3 can either be supplied to the
transmitter circuit on TEXT external input by setting bit ExtCP/TR in Transmit
Overhead Insertion 1 Control register to 1 or internally generated by setting bit
ExtCP/TR to 0. When internally generated, the transmitter calculates the parity
over 4704 payload bits of each M-frame (even parity calculation is used) and
inserts the result to Cb31, Cb32, and Cb33 bits of the next M-frame (they are all
set to the same value as the P-bits when no error insertion occurs).
FEBE (Cb4)—The three C-bits at subframe 4 (FEBE bits) can either be inserted
through the TEXT pin (when ExtFEBE/Cj-bit in the Transmit Overhead Insertion
1 Control register is set to 1), or can have an internal-automatic source (when
ExtFEBE/Cj-bit is set to 0). The internal-auto sourcing of FEBE in DS3-C-bit
parity mode is further described in
DL (Cb5)—The three C-bits in subframe 5 are assigned as a 28.2 Kb terminal-to-
terminal path maintenance data link. Their values can be taken from the TEXT
input pin when bits DLMod[2] and DLMod[1] are set to 11. The bits can all be
automatically set to 1 by setting bit DLMod [2] to 0 (DLMod [1] bit can be set to
either 0/1), or they can be chosen internally by registers generated by setting
DLMod [2] and DLMod [1] bits to 10. The last option uses an internal FIFO buffer
and the HDLC formatting mechanism to implement LAPD data link channel on
those bits. For details, see
Cb12, Cb2, and Cb6-7—Cb12 is an Nr bit (network reserved bit). The C-bits in
the second, sixth, and seventh M-subframe are reserved bits—all together, they
can either be generated internally or provided from an external pin. When bit
DLMod [0] is set to 1, those bits are taken from the TEXT pin. When this bit is set
to 0, they are all internally generated and transmitted as 1.
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CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B