CX28344 Conexant, CX28344 Datasheet - Page 76

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.1.4.1
2.1.4.2
2-30
Single Code-Word Mode
In this mode, to initiate transmission of a message byte in the TxFEAC channel, the
desired byte, in the form 0mmmxxx0 is written into the Transmit FEAC Channel Byte
register (TxFEAC [7:0]).
Each time a FEAC written message is sent (eight consecutive 1s, followed by
TxFEAC written byte), an interrupt is issued on the INTR* output pin (if interrupt is
enabled) to indicate that the last message was sent and to request a new byte from the
processor. The transmit FEAC channel Interrupt bit (TxFEACltr) at the Transmit Data
Link FEAC Status register is set high. The Transmit Data Link FEAC Status register
must be read to clear the interrupt. After sending a written message, if a new message
byte is not written to Transmit FEAC Channel Byte register, the old message is
continuously, issuing an interrupt for each time the message is sent. Interrupts from
the TxFEAC channel occur at a rate of approximately one interrupt per 1.7 ms. If a 1
is written in either the MSB or LSB position of the TxFEAC field, then continuous
transmission of idle flags (repetitive 1s) is enabled (starting after the current message
transmission is complete). No interrupts are issued until a byte of the proper format is
written to the Transmit FEAC Channel Byte register. Interrupts from the TxFEAC
channel transmitter are indicated by appearing on Transmit FEAC Channel Interrupt
bit of the framer that generated it (TxFEACltr bit).
Repetitive Code-Word Mode
In this mode, each new code word that is written to the Transmit FEAC Channel Byte
register is transmitted repetitively (eight consecutive 1s, followed by TxFEAC written
byte). Every 10 repetitive times the message is transmitted, an interrupt is issued on
the INTR* output pin (if transmitter FEAC interrupt is enabled) to request a new byte
from the processor. TxFEACltr bit at the Transmit Data Link FEAC Status register is
high. The interrupt is cleared with the reading of the Transmit Data Link FEAC Status
register. If a new byte is not written to the Transmit FEAC Channel Byte register after
an interrupt was issued, the old message is transmitted continuously (it is transmitted
for another 10 times until the Transmit FEAC circuitry checks again whether a new
message byte was written to Transmit FEAC Channel Byte register). If a new
message byte is written the transmitter first finish sending the old message and then
start sending the new written message. If a 1 is written in either the MSB or LSB
position of the TxFEAC field, continuous transmission of idle flags (repetitive 1s) is
enabled (after transmitting the last message 10 times). Interrupts are not issued until a
byte of the proper format is written to the Transmit FEAC Channel Byte register.
NOTE:
Mindspeed Technologies™
There is no TxFEAC channel transmission in either E3 mode or DS3 M13/M23 modes
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B