CX28344 Conexant, CX28344 Datasheet - Page 130

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
RxInvClk
LRxCkRis
3-18
Receive System Side Inverted Clocks—This bit controls the polarity of RXGAPCK and
REXTCK output clocks. When the bit is cleared, RXGAPCK and REXTCK rising edges are
in parallel to the data change on RXDAT pin. In this mode, both clock gaps are active low.
When this bit is set, RXGAPCK and REXTCK are inverted. The RXGAPCK and REXTCK
falling edges are in parallel to the data change on RXDAT pin. In this mode, both clock gaps
are active high.
LIU Receive Clock Polarity Control—Used to define the LINECK edge upon which the
receiver input data (on RXPOS, RXNEG pins) is clocked out by the LIU. When set, data is
sampled by the device on the falling edge of LINECK, therefore it is clocked out by the LIU
on the rising edge of LINECK. When clear, data is sampled by the chip on the rising edge of
LINECK, therefore it is clocked out by the LIU on the falling edge of LINECK.
Mindspeed Technologies™
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B