CX28344 Conexant, CX28344 Datasheet - Page 88

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.2.4.2
2-42
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Internal Processing of Overhead Bits
The internal logic is responsible for continuously identifying and monitoring the
framing bits (i.e., F-bits, M-bits, FAS, and FA) to recover, maintain, and identify loss
of frame alignment. The analysis of these bits governs identification of the Framing
Bit Error (FBE), Out of Frame (OOF), and Severely Errored Frame (SEF) indications.
DS3’s maximum average reframe time is less than 1.5 ms, and E3’s maximum
average reframe time is less than 1 ms.
Control over the frame-search mechanism is available through the RefrmStp bit in the
Feature5 Control register:
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To produce a forced reframe, the microprocessor usually needs two write cycles, the
first to write a 1 to the bit, the next to write a 0 to it. Activating this forced reframe
does not transfer the receiver into OOF. The receiver circuit actually moves its
framing template due to forced reframe only after the criteria for in frame have been
met for the new position. The status of the frame-search mechanism is open to
inspection through the ReFrm bit of the Maintenance Status register.
RAI/RDI bits (i.e., X-bits, A-bit, and RDI) are continuously monitored and their value
mirrored through the RAI/RDI indication. Similarly, FEBE/REI bits (i.e., Cb4 and
REI) are monitored and their value mirrored through the FEBE/REI indication. In
case of X-bits, any disagreement between the two bits is also noted through the X-bit
disagreement indication.
For each frame, parity is calculated according to the definitions for that frame type,
and is compared to that found in the parity/path-parity bits (i.e., P-bits, Cb3, and EM).
Any discrepancy is flagged through the parity error and path-parity error indications.
In case of P-bits, any disagreement between the two bits is noted via the P-bit
disagreement indication.
The AIC bit (Cb11) in DS3 C-bit parity is always 1; while the same bit in DS3 M13/
M23, being a justification bit, is either 0 or 1. An 8-bit register (ReceiveAICByte
Status register) containing the AIC bits from eight consecutive frames is provided for
polling and system verification of the bit.
NOTE:
In E3-G.832, the eight independently-selectable field combinations are as follows:
" FA + EM + RDI + PT
" TR
" REI
" PD/MI
" TM/SSM
" NR
" GC
" All Overhead bits + all the payload (effectively a full serial stream)
When this bit is set, no frame-search is conducted (regardless of OOF status)
When this bit has been cleared, frame-search resumes, shifted forward by one bit
from the current frame position, until a new framing is located
When this bit is clear, searching occurs in response to an OOF status
Mindspeed Technologies™
These modes are not mutually exclusive, i.e., the modes set for REXTCK and
RXGAPCK do not interfere in any way with each other or with the internal processing
of overheads).
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B