CX28344 Conexant, CX28344 Datasheet - Page 69

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.3
2.1.3.1
28348-DSH-001-B
Terminal Data Link Transmission
A terminal data link channel can be implemented over the 3 C-bits in subframe 5 in
DS3, C-bit parity mode, over the N-bit in E3-G.751 mode, and over GC byte or the
NR byte in E3-G.832 mode of operation (either GC or NR not both).
The transmitted data link bits for each mode of operation can be supplied to the
transmitter circuit externally via the data stream or on TEXT (external overhead input
pin). They can be processed internally using an internal FIFO buffer, which is
accessed, via a microprocessor-controlled interface. When the data link is disabled
and its bits are not supplied externally, the transmitter circuit automatically inserts a
default value to the transmitted data link bits: i.e. in DS3 C-bit parity mode the 3 C-
bits in subframe 5 are transmitted as 1, in E3-G.751 mode N-bit is transmitted as 1,
and in E3-G.832 when the data link is disabled on NR or GC (or both) those bytes are
transmitted as 1.
The following sections describes the transmit side terminal data link implementation
using an internal FIFO buffer. Setting bits DLMod [2:0] at the Transmit Overhead
Insertion 1 Control register as specified in Section 3.2, Feature Control registers, can
enable this mode for each rate.
For this mode of operation, the framer is equipped with a microprocessor written and
is controlled internally by a FIFO buffer and LAPD/HDLC formatting circuitry to
implement a LAPD/HDLC terminal data link transmission according to ITU-T Q.921
and ISO/IEC 3309 standards.
HDLC/LAPD Formatting Circuitry
The HDLC/LAPD formatting circuitry includes the following:
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The formatting circuitry has the capability of calculating the 16-bit Frame Check
Sequence (FCS) and transmitting it at the end of the message. Transmitting of FCS is
software-selectable by the settings of bit TxFCSEn in Transmit Data Link Control
register.
Automatic generation of FLAG sequences (01111110) when no message is being
transmitted and between messages
Zero insertion mechanism for transparency (a 0 bit is inserted after all sequences
of five continuous 1 bits in a message between two FLAGs including the FCS to
differ data from FLAG transmission)
Automatic generation of abort sequence (a sequence of 16 continuous 1 bits)
Mindspeed Technologies™
Functional Description
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