CX28344 Conexant, CX28344 Datasheet - Page 82

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.2.2
2-36
System-Side Interface
Decoding per ITU-T G.701 AMI line code involves substituting 1 for RXPOS or
RXNEG high, and 0 for RXPOS and RXNEG low (an RXPOS or RXNEG high
appearing on the same pin as the previous high [a bipolar code violation; marked as V
below] is still converted to 1).
Decoding per ITU-T G.703 B3ZS line code, involves AMI-style decoding coupled
with substitution of a 100V or 110V sequence with a 1000 sequence (a 100V
sequence appearing where a 110V is expected, or vice versa, is still converted to
1000).
Decoding per ITU-T G.703 HDB3 line code, involves AMI-style decoding coupled
with substitution of a 1000V or 1100V sequence with a 10000 sequence (a 1000V
sequence appearing where a 1100V is expected, or vice versa, is still converted to
10000).
If the clock dejitter FIFO buffer is enabled, LINECK clocks data from the line,
through the decode logic (unless bypassed), and into the dejitter FIFO buffer. The
data stream is clocked out of the FIFO buffer and through the rest of the receive logic
using RXCKI. If the clock dejitter FIFO buffer is disabled, LINECK clocks data
through the entire receiver logic, and RXCKI should be tied low.
The system-side receive interface consists of four output signals:
Either RXCKI or LINECK clocks the internal circuits (see
both output clocks (RXGAPCK and REXTCK) are derived. Output signals (RXDAT
and RXMSY) change on the rising edge of the internal clock. This is equivalent to
changing on either the rising edge or the falling edge of the output clocks (depending
on whether the output clocks are set to be non-inverted or inverted, as defined in the
RxInvClk field of the Feature5 Control register). The signals are clocked into the
system’s circuit with the opposite edge of the output clock.
RXGAPCK functionality is software-selectable to one of five modes:
The RXMSY signal has two modes based on the selection of the RxOvhMrk field of
the Feature5 register:
!
!
1.
2.
3.
4.
5.
As a frame synchronization signal, it rises from low to high on the first bit of each
frame. It returns to low after the third M-bit in DS3 mode. It returns to low after
the first Cj-bit in E3-G.751 mode, and it returns to low after the last bit of the GC
byte in E3-G.832 mode.
As an overhead marker signal, it is low on all Overhead bits and high on all
payload bits.
RXGAPCK—Data clock, gapped over user-defined bits
RXDAT—Data (all payload and overhead)
REXTC—Receive supplementary clock, software-adjustable (see
RXMSY—Frame synchronization signal
Ungapped (tick on every payload and Overhead bit)
Overhead gapped (tick on every payload bit)
Non-Cj gapped (tick on every payload and Justification Control bit)
Non-stuff gapped (tick on every payload and Stuff Opportunity bit)
Non-Cj and stuff gapped (tick on every payload, Justification Control bit and
Stuff Opportunity bit)
Mindspeed Technologies™
Section
CX28342/3/4/6/8 Data Sheet
2.), from which
Section
28348-DSH-001-B
2.)