CX28344 Conexant, CX28344 Datasheet - Page 172

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Electrical and Mechanical Specifications
Table 4-10. Motorola Asynchronous Write Cycle (MOTO* = 0)
4.3.1
4-12
FOOTNOTE:
(1)
GENERAL NOTE:
1. CX28342/CX28343/CX28344/CX28346/CX28348 are in the system but any negative edge of RD* or positive edge of WR*
Symbol
Clk is the cycle (ns) of the slowest clock (DS3—22 ns, E3—29 ns).
starts a read/write cycle.
1
2
3
4
5
6
7
8
9
A[8:0] Address setup to DS* low
A[8:0] Address hold after DS* high
R/W* low & CS* low to DS* low
DS* high to CS* high & R/W* invalid
AD[7:0] input data setup to DS* low
AD[7:0] input data hold after DS* low
DS* high to next DS* low
DS* low to DTACK* low
DS* high to DTACK* high Z
Additional Restrictions
The following restrictions apply:
!
!
!
!
When the clock source has been changed due to a setup change (RxFIFEn,
LineLp, SourceLp, PayldLp, RlineLp), the CX28342/3/4/6/8 should not be
accessed for 20 of the slowest clock cycles
After software reset, the CX28342/3/4/6/8 should not be accessed for 40 of the
slowest clock cycles.
The OneSec pulse minimal width should be 120 ns.
When output pin INTR* resets (i.e., interrupt is activated), the microprocessor
reads the Source Channel Status register. It must wait at least one-half cycle of the
slowest clock to read the updated information in th Source Channel register.
Parameter
Mindspeed Technologies™
Minimum
15
—
—
3
3
3
4
3
5
3 x clk + 15
Maximum
—
—
—
—
—
—
—
19
CX28342/3/4/6/8 Data Sheet
(1)
28348-DSH-001-B
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns