CX28344 Conexant, CX28344 Datasheet - Page 53

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Figure 2-6. DS3 System Side Transmit when TXSY is Input Signal (Frame Start)
28348-DSH-001-B
TXGAPCK(inv)
TXGAPCK
TXDATI
TXCKI
TXSY
Subframe 6
84 Payload bits
The behavior of TXGAPCK signal is shown both in normal (TXGAPCK) and in
inverted mode (TXGAPCK). Since none of the overheads are set to be inserted with
payload, TXGAPCK is gapped during all Overhead bits illustrated in
through 2-6.
Transmit Operation in E3-G.751 Mode
During E3-G.751 mode of operation, TXCKI pin is connected to a 34.368 MHz clock.
When TXSY signal is provided externally, it should have a low-to-high transition
from the last bit of the E3-G.751 frame to the first bit of the next frame.
When the TXSY is provided internally and used as a frame start synchronization
signal, it has a low-to-high transition at the same place. TXSY output returns to low
after the C11 justification bit, as illustrated in
If TXSY is used as an overhead indication output signal, TXSY is low during all
Overhead bits positions and high during data bits position regardless of Overhead bits
source.
Figure 2-7
in inverted mode (TXGAPCK). Identical to the DS3 mode, the signal is sampled from
the falling edge of TXCKI. In this figure, Justification Control bits are set to be
supplied with the data stream, TXGAPCK is gapped only during FAS, A, N-bits, and
Stuff Opportunity bits, and supplies clock pulses during the payload and Justification
Control bits (C
illustrates the TXGAPCK clock behavior both in normal (TXGAPCK) and
Mindspeed Technologies™
M3
j
1, C
j
2, C
The full behavior is not
679 bits of Subframe 7 including its
shown for this section
j
3 where
Subframe 7
overhead bits
j
= 1 to 4).
Figure
2-7.
X1
Subframe 1
84 Payload bits
Functional Description
Figures 2-4
100542_009
2
-
7