CX28344 Conexant, CX28344 Datasheet - Page 123

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Default after reset: 00(h)
Direction: Read/Write
Modification: Dynamic
SEFStrtIE
LOSStrtIE
IdleStrtIE
YelStrtIE
AISStrtIE
OOFStrtIE
28348-DSH-001-B
Reserved
7
Reserved
Severely Errored Frame Start Interrupt Enable—Set to enable interrupts to be asserted on
INTR* pin due to detection of SEF event start in DS3 mode. When the receiver detects an SEF
condition start, the interrupt is asserted and the SEFStrt bit in Alarm Start Interrupt Status
register is set. When this bit is cleared, detection of SEF start sets the appropriate status bit,
however an interrupt is not activated. This bit has no effect in E3-G.751 and E3-G.832 modes.
Loss of Signal Start Interrupt Enable—Set to enable interrupts to be asserted on INTR* pin,
due to a detection of LOS condition start in all modes. When a LOS condition start is detected,
the interrupt is asserted and the LOSStrt bit in Alarm Start Interrupt Status register is set.
When this bit is cleared, detection of LOS start sets the appropriate status bit; however, an
interrupt is not activated.
Idle Interrupt Start Enable—Set to enable interrupts to appear on INTR* due to detection of
Idle event start in DS3 mode. When the receiver detects an Idle start, the interrupt is asserted
and the IdleStrt bit in Alarm Start Interrupt Status register is set. When this bit is cleared,
detection of Idle start sets the appropriate status bit; however, an interrupt is not activated.
This bit has no effect in E3-G.751 and E3-G.832 modes.
Yellow Alarm Start Interrupt Enable—Set to enable interrupts to be asserted on INTR* due to
detection of RAI/RDI event start in all modes. When the receiver detects an RAI/RDI event
start, the interrupt is asserted and YelStrt bit in Alarm Start Interrupt Status register is set.
When this bit is cleared, detection of RAI/RDI start sets the appropriate status bit; however, an
interrupt is not activated.
Alarm Indication Signal Start Interrupt Enable—Set to enable interrupts to be asserted on
INTR* due to detection of AIS event start in all modes. When the receiver detects an AIS
event start, the interrupt is asserted and AISStrt bit in Alarm Start Interrupt Status register is
set. When this bit is cleared, detection of AIS start sets the appropriate status bit; however, an
interrupt is not activated.
Out of Frame Start Interrupt Enable—Set to enable interrupts to be asserted on INTR* pin due
to detection of OOF condition start in all modes. When the receiver detects an OOF condition
6
Dual-Edge Interrupt Control Registers
The Dual-Edge Interrupt Control registers enable event detection as the source of an
interrupt. The events are of a continuous type. Enabling the dual-edge interrupt causes
assertion of an interrupt, due to detection of the event’s start or to detection of the
event’s end. To enable an interrupt’s appearance on the INTR* pin due to a particular
event’s start or end, the control bit corresponding to this event’s start or end must be
set high in these registers. If an event’s start or end has its interrupt control bit set low,
then interrupts due to this event’s start or end are masked from appearing on INTR*.
The reason for the dual-edge interrupt assertion can be viewed in the Dual-Edge
Interrupt status registers.
Alarm Start Interrupt Control Register (CR02i)
SEFStrtIE
5
Mindspeed Technologies™
LOSStrtIE
4
IdleStrtIE
3
YelStrtIE
2
AISStrtIE
1
OOFStrtIE
0
Registers
3
-
11