CX28344 Conexant, CX28344 Datasheet - Page 62

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.1.1.3
2-16
E3–G.832 Mode
E3-G.832 frame structure comprises seven octets of Overhead bits. They are divided
into the following:
!
!
!
!
!
!
In E3-G.832 mode, the framer provides two options for the insertion of the frame
overhead bytes within the data stream: either all frame Overhead bits are inserted with
the data stream (by setting bit ExtDat to 1), or none of the Overhead bits are inserted
via the data stream (setting bit ExtDat to 0).
When the frame Overhead bits are not chosen to be inserted via the data stream, the
following source options are provided for each group of frame Overhead bits:
!
!
!
!
!
FA1 and FA2 (2 octets)
Error Monitoring byte (EM)
Trail Trace byte (TR)
Maintenance and Adaptation byte (MA)
Network operator byte (NR)
General purpose communication channel byte (GC)
FA1 and FA2—The frame alignment bytes that have the value of FA1 = 11110110
(transmitted left to right), FA2 = 00101000 (transmitted left to right) are
automatically inserted by the framer’s transmitter circuit at the beginning of each
frame or inserted from the TEXT pin by setting ExtFrm A1 bit.
EM—Error monitoring, BIP-8 byte. When not all overheads are inserted via the
data stream, this byte is generated automatically by the transmitter circuit. The
transmitter calculates a BIP-8 code using even parity. The BIP-8 is calculated over
all bits, including the Overhead bits, from the previous frame. The computed BIP-
8 is placed in the EM byte of the current transmitted E3-G.832 frame.
TR—The trail trace byte to be transmitted can be either supplied externally on the
TEXT pin (by setting ExtCP/TR bit at the Transmit Overhead Insertion 1 Control
register to 1) or disabled and automatically transmitted as all 0s (by setting ExtCP/
TR bit to 1).
MA RDI—Bit 1 of the MA field is the remote defect indicator. This bit value can
either be generated automatically, controlled by a register or inserted through
TEXT pin, depending on AutoRAI, TxAlm, and ExtRAI bit settings. If AutoRAI
= 1, automatic RDI is enabled. In this mode, for as long as Loss of Signal (LOS) or
loss of frame alignment—Out of Frame (OOF) conditions are detected at the
receiver, the transmitter automatically inserts 1 at the transmitted RDI-bit.
Otherwise, the RDI-bit is transmitted as 0. RDI insertion is also controlled by
TxAlm [1] bit at the Mode Control register. Normally, the transmitter sends 0 as
the RDI-bit. When AutoRAI = 0, setting ExtRAI bit at the Transmit Overhead
Insertion 2 Control register to 1 causes RDI-bit insertion through TEXT pin. For
as long as TxAlm[1] is set to 1, RDI-bit contains 1, regardless of other RDI-bit
sourcing settings.
MA REI—Bit 2 of the MA field is the remote error indication. It can be either
generated internally or supplied on the TEXT pin to the transmitter circuit. If bit
ExtFEBE/Cj in Transmit Overhead Insertion 1 Control register is set to 1, REI-bit is
inserted to the transmitter via the TEXT pin. If bit ExtFEBE/Cj is set to 0, REI is
internally generated automatically. In the internal-automatic mode the REI-bit is set
by the transmitter as a reaction to an error detected in a received BIP-8 code (in EM
field). In this mode, if the received BIP-8 code at the current frame does not equal
the calculated BIP-8 code over the previously received frame, the transmitter inserts
1 at the REI-bit for one frame at the first opportunity. As long as no BIP-8 errors are
detected at the received frame, the tra3nsmitter inserts 0 at the transmitted REI-bit.
Mindspeed Technologies™
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B