CX28344 Conexant, CX28344 Datasheet - Page 97

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.2.7.1
28348-DSH-001-B
These interrupts are independently enabled by setting the RxNFIE, RxMsgIE, and
RxOVRIE fields in the Receive Data Link Control register, and are differentiated by
reading the Status Indication register (Receive Data Link Status register).
The RDL-related status indications available are as follows:
!
!
!
!
!
These indications are detected by examining RxNF, RxMsg, RxOVR, RxBlk, and
StatByte fields (respectively) of the Receive Data Link Status register.
Initial Setup
On reset, the RDL is disabled, with no interrupts active. Prior to enabling the RDL,
the desired interrupt enables the Near-Full FIFO threshold, and the RDL related
options should be set to the desired values through the Receive Data Link and the
Receive Data Link Threshold Control registers. Checking the 16-bit FCS is
software-selectable by setting the RxFCSEn field of the Receive Data Link Control
register. If the channel is functioning in E3-G.832 mode, the NRDL field of the
Receive Data Link Control register should be set to identify which of the two possible
overhead bytes (NR or GC) is processed by the RDL.
Setting the RxDLEn field of the Receive Data link Control register activates the RDL.
Once active, the HDLC related functionality (flag and abort detection, zero removal)
of the RDL is automatically executed on all DL data flowing through the FIFO buffer.
Once the RDL is enabled, it assumes the channel is idle and starts looking for HDLC
flag sequences.
To modify the basic settings of the RDL (i.e., Near-Full FIFO threshold, FCS
checking, E3-G.832 NR/GC source), the system should first disable the RDL (by
clearing the RxDLEn field of the Receive Data Link Control register).
After disabling the RDL, when accompanied by an immediate termination of all its
activities, the following enable causes discard of all the FIFO contents and update of
the status indications to represent a new status (i.e., all interrupt indications clear, no
data blocks in the FIFO buffer).
FIFO near-full (set and cleared with the interrupt)
Message received (set and cleared with the interrupt)
FIFO overrun (set and cleared with the interrupt)
Data block in FIFO (set if there is 1 complete data block in the FIFO, otherwise
cleared)
Type of next FIFO byte (set if status, cleared if data; undefined if the Data block in
FIFO indication is not set)
Mindspeed Technologies™
Functional Description
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