CX28344 Conexant, CX28344 Datasheet - Page 149

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CX28344

Manufacturer Part Number
CX28344
Description
(CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
Manufacturer
Conexant
Datasheet
CX28342/3/4/6/8 Data Sheet
Value after reset: 03(h)
Direction: Read only
Value after enable: 03(h)
Bit [7] is undefined
TxFEACltr
TxFull
TxMsg
TxUR
TxNE
TxEmpty
28348-DSH-001-B
7
Reserved
Transmit FEAC Channel Interrupt—In DS3-C Bit Parity mode, set high indicating that the
transmitter is ready for a new byte to be written to the Transmit FEAC Channel Byte register.
When FEAC single mode, this happens after every code word transmission start. When in
FEAC repetitive mode, this happens after the transmitter has started sending the code word 10
consecutive times for the first time. Cleared when this register is read.
In DS3-M13/M23, E3-G.751, and E3-G.832 modes, this bit should be ignored.
Transmit Data Link FIFO is Full—Set when the transmit FIFO contains 128 bytes. Cleared
when there are less than 128 bytes in the transmit FIFO (i.e., this bit is high and the first byte is
read). No interrupt is linked to this bit.
Transmit Data Link Message Transmitted Event—Set when the final bit of the closing flag of
a message is transmitted. Cleared when this register is read.
Transmit Data Link Underrun Error—Set when the transmit FIFO buffer is empty and the
transmit circuit tries to read another byte from it, i.e., the microprocessor does not meet the
requirements and does not fill the FIFO buffer properly. Cleared when this register is read.
Transmit Data Link Near-Empty Event—Set when TxNEThr bytes or less are left in the FIFO.
Cleared when the number of bytes in the FIFO is greater than TxNEThr.
Transmit Data Link FIFO is Empty—Set when the FIFO is empty, i.e., the last byte is read
from it. Cleared when set and the first write by the microprocessor (after being empty) is done.
No interrupt is linked to this bit.
6
Transmit Data Link FEAC Status Register (SR08i)
TxFEACltr
5
Mindspeed Technologies™
TxFull
4
TxMsg
3
TxUR
2
TxNE
1
TxEmpty
0
Registers
3
-
37

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