CX28344 Conexant, CX28344 Datasheet - Page 121

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Default after reset: 00(h)
Direction: Read/Write
Modification: Bits 4–7: dynamic, bits 0–1: static
LineLp
SourceLp
TxAlm1,0
E3Frm
CbitP/832
28348-DSH-001-B
LineLp
7
SourceLp
Shallow Line Loopback Enable—Set to enable loopback in the external direction (back to
network). This loopback connects the received data stream before B3ZS/HDB3 decoding to
the transmitter. All data and overhead bits are looped, and Bipolar Code Violations (BPVs) are
fully preserved per ANSI standard T1.404. The received data is presented to all receiver
blocks, and is present on the receiver output pins.
A dynamic change of this bit can cause loss of data for a few clock cycles, until the channel is
internally synchronized. Activation or deactivation of a loopback causes internal circuits to
switch between clocks. After writing this bit, the microprocessor should not access any of the
device registers (read/write) for 20 slowest clock cycles.
Source Loopback Enable—Set to enable the loopback in the internal direction. This loopback
connects the encoded transmitter data and clock directly to receiver B3ZS/HDB3 decoder.
Transmission of data on the line is not affected by this loopback.
A dynamic change of this bit can cause loss of data for a few clock cycles, until the channel is
internally synchronized. Activation or deactivation of a loopback causes internal circuits to
switch between clocks, after writing to this bit, the microprocessor should not access any of
the device registers (read or write) for 20 slowest clock cycles.
Transmit Alarm Control—Used to control transmission of various alarm signals. In DS3
mode, AIS, idle, and yellow alarm signals on the outgoing DS3 stream are controlled as
follows:
In E3-G.751 and E3-G.832 modes, the TxAlm0 bit is set high to transmit the E3 AIS signal.
The TxAlm1 bit is set high to transmit the E3 yellow alarm (A-bit or RDI bit high). TxAlm0
bit has precedence in E3 mode.
E3 Framing Mode—Enables the E3 mode framing and transmission circuitry. When cleared,
DS3 mode is active. The specific framing format is defined according to CbitP/832 bit.
C-Bit Parity/E3-G.832 Mode—Selects which type of framing is present on the transmitted
DS3/E3 signal.
6
Channel Control Registers
The index letter i, appearing in the registers’ name, represents the channel number,
one per channel.
Mode Control Register (CR00i)
TxAlm1
5
TxAlm1
0
0
1
1
Mindspeed Technologies™
TxAlm0
4
TxAlm0
0
1
0
1
Reserved
3
Normal, No Alarms Transmitted
Yellow Alarm (X-bits low) Transmitted
Idle Code Transmitted
AIS Transmitted
Reserved
2
Alarm Action
E3Frm
1
CbitP/832
0
Registers
3
-
9