CX28344 Conexant, CX28344 Datasheet - Page 169

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Table 4-7. Intel Asynchronous Read Cycle (MOTO* = 1)
Figure 4-8. Intel Asynchronous Write Cycle (MOTO* = 1)
28348-DSH-001-B
FOOTNOTE:
(1)
(2)
(3)
AD[7:0]
Symbol
WR*
Clk is the cycle (ns) of the slowest clock (DS3—22 ns and E3—29 ns).
The transition must be completed, i.e., RD* must rise after AD[7:0] is valid.
CS* can be kept low if only CX28342/CX28343/CX28344/CX28346/CX28348 is in the system, but negative edge of RD* or
positive edge of WR* starts a read/write cycle.
ALE
A[8]
RD*
CS*
10
11
1
2
3
4
5
6
7
8
9
ALE high pulse width
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
ALE low to RD* and CS* both low
WR* high to CS* low
CS* low to RD* low
RD* high to CS* high
CS* high to WR* low
RD* low to AD[7:0] valid
RD* high to AD[7:0] invalid or three-state
RD* high to next ALE low
Parameter
Address
Address
1
2
2
Mindspeed Technologies™
3
3
12
More than A[8], AD[7:0]
4
5
Minimum
hold time
15
—
15
5
5
3
3
3
3
0
8
Write Data
9
Electrical and Mechanical Specifications
3 x clk + 20
6
Maximum
10
10
—
—
—
—
—
—
—
—
—
11
7
(1)
Units
100542_029
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
-
9