CX28344 Conexant, CX28344 Datasheet - Page 89

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
Internal processing of the terminal data link bits (i.e., Cb5, N-bit, NR, and GC) as
HDLC/LAPD channels makes their contents available to the system through an
internal 128-byte FIFO buffer; this mechanism is fully described in
possible to use this internal mechanism for non-HDLC channels.
Messages flowing on the FEAC (Cb13) channel are supplied to the system via a
dedicated register.
Non-alarm fields of the MA byte (i.e., PT, PD/MI, and TM/SSM) are available for
inspection through the microprocessor interface. Their contents (three bits for PT, two
bits for PD/MI, one bit for TM, and four bits for SSM) are saved on every E3-G.832
frame in dedicated registers (RxMAPT, RxMAPD, and RxMATM fields of the E3-
G.832 MAFields Status register; RxSSM field of the E3-G.832 SSMField Status
register). The host processes poll these fields to detect changes in their values. The
RxSSM field, on a multiframe boundary (i.e., when MI is 11), stores the 4-bit SSM
field, spread over a four-framed multiframe based on the MI field. Selection of
whether the framer functions in TM or SSM mode is through the SSMEn field of the
Feature4 Control register.
There is no internal processing of justification control, stuff opportunity, reserved,
and TR fields.
Mindspeed Technologies™
Section 2.
Functional Description
It is not
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