CX28344 Conexant, CX28344 Datasheet - Page 114

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
3-2
A third variant of modification is available in relation to the datalink channel and is
termed datalink static (DL-static). These bits can be modified dynamically only if the
internal datalink mechanism is disabled:
!
!
The same applies to the OneSecMod-static modification. (These bits can be modified
dynamically, but only when the One Second mode is disabled.).
When the channel is disabled via software, the control bits are unchanged to avoid
interrupt assertion the channel’s interrupts and should be masked via software. To
clear a status register while a channel is disabled, the software should read the
registers and execute the required operations. Enabling a channel can affect some of
the status registers. The values after enable are detailed in the following paragraphs.
Some registers are described as unaffected by enabling the channel, because they are
not affected directly by the enable bit. However, they may be affected by other
registers, which may be affected by the channel’s enable bit.
NOTE:
Rx bits: when the RxDLEn field in the Receive Data Link Control register is
cleared
Tx bits: when the DLMod fields in the Transmit Overhead Insertion Control
register is set, so that HDLC and FIFO mechanism is disabled and does not affect
the DL channel
Mindspeed Technologies™
In the following paragraphs the term set means logic 1, and the term cleared means
logic 0. Reserved bits with defined values are marked with Rsvd, and their value is 0.
Reserved bits with undefined values are marked with - -.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B