CX28344 Conexant, CX28344 Datasheet - Page 71

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.3.3
28348-DSH-001-B
TDL FIFO Related Status Bits
The TDL FIFO status indications are available at the Transmit Data Link FEAC
Status register to be read by the microprocessor. They are as follows:
!
!
!
!
!
Initial Setup of Transmit Data Link
The TDL is disabled on reset, with no interrupts active. Bits DLMod [2:0] in the
Transmit Overhead Insertion 1 Control register control TDL enabling for each mode.
The desired interrupt settings, for the Near-Empty FIFO threshold, and the
TDL-related options should be set to the desired values through the Transmit Data
Link and the Transmit Data Link Threshold Control registers. The insertion of the
FCS is software-selectable by setting the TxFCSEn field of the Transmit Data Link
Control register.
When only the Data Link is disabled, the FIFO buffer is cleared, and the Near-Empty
and Empty status bits are read. If the Near-Empty interrupt is enabled, a Near-Empty
interrupt is generated. Before disabling the Data Link, the user should mask its
interrupts. If the channel is enabled when disabling the Data Link a repetitive 1s
signal is sent. While the Data Link is disabled, the FIFO buffer can still be written.
When both the Data Link and the channel are enabled, if the FIFO buffer is not reset
and is not empty, a new message starts after sending two FLAG sequences. If the
FIFO buffer is empty, FLAG sequences are automatically transmitted until a new
message byte is written to the FIFO buffer.
When the entire channel is enabled after reset or disabled (while data link is enabled),
the FIFO buffer is cleared, the Near-Empty and Empty status bits are led and if the
Near-Empty interrupt is enabled a Near-Empty interrupt is generated.
When the whole channel is disabled, the following occurs:
!
!
!
!
TDL FIFO Near-Empty—(set and cleared with the interrupt) (indicated by TxNE
bit)
TDL FIFO empty—This status indicates that the FIFO buffer is empty and has no
message bytes written to it (indicated by TxEmpty bit).
TDL FIFO underrun – (set and cleared with interrupt) (indicated by TxUR bit)
TDL message transmitted—(set and cleared with interrupt). This status indicates
that a full message was transmitted including its closing FLAG (indicated by
TxMsg bit).
TDL FIFO full—An indication bit that is set and stays set as long as the FIFO
buffer is full—128 bytes are stored inside the FIFO buffer. The FIFO full status
can be used in polling mode to check if the FIFO buffer is full and there is no point
in writing to it (indicated by TxFull bit).
Data Link activities are terminated.
Data link control settings at the Transmit Data Link and the Transmit Data Link
Threshold Control registers are not affected (interrupt enables, Near-Empty
threshold, FCS transmission, etc.).
The channel’s old status at the Transmit Data Link FEAC Status register is
maintained (status bits maintain their old values and so do interrupts if not
disabled earlier).
The FIFO buffer is not emptied.
Mindspeed Technologies™
Functional Description
2
-
25