CX28344 Conexant, CX28344 Datasheet - Page 125

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
3.4
Default after reset: 07(h)
Direction: Read/Write
Modification: Bits 0–2: dynamic; bits 5–7: static
TxAMI
RxAMI
NRZMod
FEBEC/PT[1:3]
28348-DSH-001-B
TxAMI
7
Transmit AMI Mode—Set high to enable AMI line coding on TXPOS and TXNEG (no B3ZS/
HDB3 encoding or decoding). When cleared, B3ZS/HDB3 line coding is used on these pins.
This bit is effective only when NRZMod bit is cleared.
Receive AMI Mode—Set high to enable AMI line coding on RXPOS and RXNEG (no B3ZS/
HDB3 encoding or decoding). When cleared, these pins use B3ZS/HDB3 line coding.
NRZ Mode—Set high to disable bipolar (B3ZS/HDB3 or AMI) encoding or decoding and
provide a unipolar NRZ line code on TXPOS/TXNEG and RXPOS/RXNEG. Setting this bit
disables and bypasses the encoder and decoder circuits. The unipolar output appears at the
TXPOS pin while TXNEG pin is continuously low and the clock is available on TCLKO pin.
The unipolar input should appear on RXPOS, while RXNEG can be tied to the LCV output of
the LIU and be used as an increment control of the LCV counter.
FEBE Pattern/Payload Type Bit Field—In DS3 mode set to the 3-bit sequence that is sent each
time a FEBE indication is transmitted in C-bit parity mode. This pattern is automatically
transmitted when the ExtFEBE/Cj bit in the Transmit Overhead Insertion 1 Control register is
cleared, and the receiver detects a framing or path parity error. This pattern must not be all-1s
to indicate a FEBE to the far end. An all-1s pattern disables FEBE transmission and should not
be used for any other purpose. In E3-G.832 mode set to the 3-bit pattern that is transmitted
every frame in the payload type field in the MA byte.
In both modes, FEBEC/PT[1] bit is transmitted first and FEBEC/PT[3] bit is transmitted last.
In both modes, writing a new value to this byte takes effect only starting from the next
RxAMI
Feature Control Registers
6
The set of Feature Control registers is provided to enable or disable miscellaneous
features in the CX2834i devices.
Feature1 Control Register (CR04i)
NOTE:
NRZMod
NRZMod
5
0
0
0
0
1
Mindspeed Technologies™
This bit is effective only when NRZMod bit is cleared.
RxAMI
Reserved
0
1
X
X
X
4
TxAMI
X
X
X
0
1
Reserved
3
B3ZS/HDB3 encoded data on RXPOS, RXNEG
AMI encoded data on RXPOS, RXNEG
B3ZS/HDB3 encoded data on TXPOS, TXNEG
AMI encoded data on TXPOS, TXNEG
NRZ data on TXPOS, RXPOS; TXNEG is set to zero;
RXNEG is used as an LCV input from the LIU (if
unused, should be tied low)
FEBEC/PT[1]
2
Description
FEBEC/PT[2]
1
FEBEC/PT[3]
0
Registers
3
-
13