CX28344 Conexant, CX28344 Datasheet - Page 136

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Default after reset: 00(h)
Direction: Read/Write
Modification: Bits 1–3: dynamic, bits –DL: static
TxMsgIE
TxURIE
TxNEIE
TxFCSEn
Default after reset: 00(h)
Direction: Read/Write
Modification: DL—static
TxNEThr[6:0]
3-24
Reserved
Reserved
7
7
TxNEThr[6]
Reserved
Transmit Data Link Message Transmitted Interrupt Enable—Set to enable interrupt assertion
on INTR* pin due to end of transmission of a full message, see
Transmit Data Link FIFO Underrun Interrupt Enable—Set to enable interrupt assertion on
INTR* pin due to Data Link FIFO underrun error, see
Transmit Data Link FIFO Near-Empty Interrupt Enable—Set to enable interrupt assertion on
INTR* pin due to the FIFO buffer being near empty, see
Transmit Data Link FCS Calculation Enable—Set to enable FCS calculation over the
transmitted message and add it to the end of the transmitted message. When cleared, the FCS
calculation and addition are executed by the software.
Transmit Data Link FIFO Near Empty Threshold—Set to the threshold value, used to indicate
a near-empty FIFO event. The range of values available for this purpose is 0–126, where 00(h)
is interpreted as 0, 01(h) is 1 …etc. and 7E(h) is interpreted as 126.
6
6
Transmit Data Link Control Register (CR13i)
The Transmit Data Link Control register (CR13i) enables different modes and
interrupts in the Transmit Data Link operation.
NOTE:Reserved bits in Control registers must be set to zero.
Transmit Data Link Threshold Control Register (CR14i)
TxNEThr[5]
Reserved
5
5
Mindspeed Technologies™
TxNEThr[4]
Reserved
4
4
TxNEThr[3]
TxMsgIE
3
3
Section
TxNEThr[2]
TxURIE
Section
2
2
2.1.3.
Section
2.1.3.
TxNEThr[1]
TxNEIE
2.1.3.
CX28342/3/4/6/8 Data Sheet
1
1
28348-DSH-001-B
TxNEThr[0]
TxFCSEn
0
0