CX28344 Conexant, CX28344 Datasheet - Page 134

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Registers
Default after reset: 00(h)
Direction: Read/Write
Modification: Static
ExtReserved/GC
ExtDL/NR
ExtFEBE/A
ExtCP/TM
ExtFEAC/PD/Stf
ExtAIC/Cj/TR
ExtFrm
3-22
ExtReserved/
GC
7
ExtDL/NR
External Reserved C-bits/GC Byte—Set to enable presentation of reserved C-bits (C12, C2,
C6, C7) in DS3-C Bit Parity mode or presentation of GC byte in E3-G.832 mode through
REXTCK pin. In DS3-M13/M23 and E3-G.751 modes, this bit is ignored.
External Data Link/NR Byte—Set to enable presentation of data link data through REXTCK
pin. The bits are output exactly as they were received (i.e., the HDLC circuit is bypassed). In
DS3-C Bit Parity mode, this bit enables presentation of C5 bits through REXTCK pin. In E3-
G.751 mode, this bit enables presentation of N-bit through REXTCK pin. In E3-G.832 mode,
this bit enables presentation of NR byte through REXTCK pin. In DS3-M13/M23, this bit is
ignored.
External FEBE/REI/A-Bit—Set to enable presentation of FEBE field in DS3-C Bit Parity
mode or REI bit field in E3-G.832 mode through the REXTCK pin. In E3-G.751 mode, set to
enable presentation of A-bit through REXTCK pin. In DS3-M13/M23 mode, this bit is
ignored.
External Path Parity/Timing Marker/SSM—Set to enable presentation of CP field in DS3-C
Bit Parity mode or Timing Marker/SSM bit field in E3-G.832 mode through REXTCK pin.
In DS3-M13/M23 and E3-G.751 modes, this bit is ignored.
External FEAC/Payload Dependent/Multiframe Indicator/Stuff Opportunity Bits—Set to
enable presentation of FEAC channel in DS3-C Bit Parity mode or payload dependent/
multiframe indicator field in E3-G.832 mode or Stuff Opportunity bits in DS3 M13/M23 and
in E3-G.751 modes through REXTCK pin.
External AIC/Justification Control/Trail Trace—In DS3-C Bit Parity mode, set to enable
presentation of application identification channel through REXTCK pin. In DS3-M13/M23
and E3-G.751 modes, set to enable presentation of the Justification Control bits through the
REXTCK pin. In E3-G.832 mode, set to enable presentation of Trail Trace byte through
REXTCK pin.
External Framing Fields—In DS3 modes, set to enable presentation of M, F, X, and P-bits
through the REXTCK pin. In E3-G.751 mode, set to enable presentation of FAS field through
the REXTCK pin. In E3-G.832 mode, set to enable presentation of FA1, FA2, EM, RDI, and
PT fields through REXTCK pin.
6
REXTCK Control Register (CR11i)
The REXTCK Control register provides enabled marking of different fields through
REXTCK pin. Presentation of a field through REXTCK pin does not prevent it from
being ticked upon by the RXGAPCK pin or from being processed via the
microprocessor interface. Setting a bit in this register does not affect other control bits
set in other registers. This enables monitoring of certain fields for testing, in addition
to being processed by another mechanism. If a specific field should be presented only
through the REXTCK pin, it should be disabled from being presented on RXGAPCK/
microprocessor interface in another control register.
ExtFEBE/A
5
Mindspeed Technologies™
ExtCP/TM
4
ExtFEAC/PD/
Stf
3
ExtAIC/Cj/TR
2
ExtFrm
CX28342/3/4/6/8 Data Sheet
1
28348-DSH-001-B
AllRxExt
0