CX28344 Conexant, CX28344 Datasheet - Page 102

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2-56
In both modes, no allowance is made for bit errors in the code overhead. Complete
code word patterns can be separated from one another by any amount of data (whether
all-1s or not), which are ignored by the RFEAC logic.
In both detection schemes, a valid idle signal is detected when 16 consecutive 1s are
located.
The RFEAC is always in one of two internal states, namely idle state (the initial state)
or message state:
!
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As a FEAC message takes 16 DS3 frames, new FEAC message interrupts arrive at a
maximal rate of 1 per 1.7 ms for single code word detection, and at a maximal rate of
1 per 17 ms for multiple code word detection.
There is no facility for disabling the RFEAC circuitry; systems that do not need to
receive this information should not enable the two RFEAC interrupts. Similarly,
systems that work by polling should also mask the interrupts and poll the interrupt
identification bits. Masking and unmasking is performed by setting the RxFEACIE
and RxFEAC IdleIE fields of the Feature3 Control register.
In addition to the interrupt based FEAC mechanism described above, a three-stage
FIFO buffer (called “FEAC stack”) for FEAC messages is provided to allow for a
more relaxed and flexible FEAC channel processing.
The FEAC stack mechanism provides a register (Receive FEAC Stack byte) for the
stacks’ FEAC message with two extra bits. One extra bit signaling that the data is
valid and has not been read and another bit signaling that there are more valid
messages in the stack. If the valid bit is off, it forces the more bit to zero and the six
FEAC message bits are set to undefined.
If the more bit is off, it means there are no more valid messages. An indication that the
stack is not empty is provided by and implemented in the FEAC Status register bit
RxFEACSNE. When this status bit is set, an interrupt is generated unless the interrupt
has been masked. (the RxFEACSNEIE bit in the Feature3 Control register is off.) The
stack has no alert on under run and over run. A word shifted into a full stack can
overrun an old word that has not been read yet. Reading an empty stack results in
reading an undefined code word except for valid bit and more bit which are zero.
NOTE:
In idle state, the RFEAC scans for a valid code word (according to one of the two
definitions given above). Once this is found, the valid code word proper (plus the
two 0s) is written to the Receive FEAC Byte Status register, and a new FEAC
message interrupt (with the RxFEACItr indication of the Receive Data Link FEAC
Status register) is generated (it is cleared once the code word proper is read from
Receive FEAC Byte Status register). This moves the RFEAC to message state.
In message state, the RFEAC scans for either a valid code word or a valid idle
signal. If a valid code word is found, processing is the same as in idle state. If a
valid idle signal is detected instead, a reversion to idle interrupt (with the RxFEAC
Idle indication of the Receive Data Link FEAC Status register) is generated (it is
cleared once the interrupt indication is read); this moves the RFEAC back to idle
state.
Mindspeed Technologies™
There is no buffering of messages; if the system fails to read the code word proper
from the Receive FEAC Byte Status register before a new one is located, the old code
word is overwritten.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B