CX28344 Conexant, CX28344 Datasheet - Page 77

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.5
2.1.5.1
28348-DSH-001-B
Test Equipment—Error Insertion
The CX28342/3/4/6/8 framer provides the ability to insert errors intentionally in the
transmitted data stream (for each framer individually) by using the Error Insertion
Control registers. The Error Insertion register contains a control bit for each available
error. Setting the relevant bit at the Error Insertion Control registers causes insertion
of one requested error at the next valid opportunity for each error. Once the error is
inserted, the relevant control bit is automatically cleared. Several different error
insertions can be set at the same time by setting more than one error control bit; each
error selection is cleared when the appropriate error is inserted. Before setting the
control bits for another error insertion, they must be polled and the relevant control
bits, for the desired errors, should be checked for zero. Writing zero to the control bits
does not affect their settings.
The errors that can be inserted, and their effect on the transmitted data, are specified
for each basic mode of operation.
DS3 Mode
In DS3 mode (both in M13/M23 and in C-bit parity mode), errors listed in
can be transmitted by setting bits at the Error Insertion1 Control register.
Table 2-4. Setting the Error Insertion1 Control Register in DS3 Mode (1 of 2)
Framing F
Framing M
P-bit Parity
P-bit parity
disagreement
CP bit error
(path parity)
RAI
X-bit
disagreement
Error
(1)
Mindspeed Technologies™
FrmErrF
FrmErrM
ParErr
ParDgrErr
CPErr
YelErr
XdgrErr
Bit
Set to
1
1
1
1
1
1
1
A single F-bit error is inserted by inverting the next
transmitted F-bit (only one bit).
A single M-bit error is inserted by inverting the next
transmitted M-bit (one M-bit).
Transmission of incorrect value in the two P-bits (i.e.,
incorrect parity calculation over the previous frame).
In this case, the next two P-bits of a single frame to be
transmitted are inverted.
Transmission of unequal P-bits at the next opportunity
(performed by inverting the next transmitted P-bit).
Transmission of an incorrect value in the three CP bits
in an M-frame. It is performed by inverting the three
CP bits of a single M-frame at the next opportunity.
Transmission of the opposite value of the M-frame X-
bits than the expected/set value. This is performed by
inverting the two X-bits transmitted of a single M-
frame at next opportunity. Thus, if RAI is set to be
transmitted, the X-bits are set to 1 (instead of 0). If
RAI alarm is not set to be transmitted, both X-bits are
transmitted as 0 (instead of 1).
Transmission of opposite values of both X-bits in an
M-frame. The setting of XdgrErr to 1 causes the two
X-bits of a single M to be transmitted with opposite
values by inverting the next X-bit to be transmitted.
Description
Functional Description
Table 2-4
2
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31