CX28344 Conexant, CX28344 Datasheet - Page 137

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Default after reset: Undefined
Direction: Read/Write
Modification: Dynamic
TxDLMsg [7:0]
Default after reset: 00(h)
Direction: Read/Write
Modification: Bits 0, 2–4: dynamic, bits 1, 5: DL-static
NRDL
RxOVRIE
RxMsgIE
RxNFIE
RxFCSEn
RxDLEn
28348-DSH-001-B
TxDLMsg[7]
Reserved
7
7
TxDLMsg[6]
Reserved
Transmit Data Link Message Byte—This byte is loaded with data to be written into the Data
Link FIFO buffer, which is later transmitted by the Data Link Transmitter circuit. Two
addresses are allocated for this register. During the whole message, excepting the last byte, the
lower address is used to access this register. When the last byte of the message is written to this
register, the higher address is used. The higher address indicates the end of the message to the
transmitter circuit. TxDLMsg [0] bit is transmitted first and TxDLMsg [7] bit is transmitted
last. Reading this register causes latching of the content of the FIFO stage pointed by the
Transmit Data Link Read pointer into this register.
NR Byte Over the Data Link—This bit is effective only in E3-G.832 mode. When set, selects
NR byte to be processed by the receiver data link HDLC and FIFO circuits. When cleared,
selects GC byte to be processed by the receiver data link HDLC and FIFO circuits.
Receive Data Link FIFO Overrun Interrupt Enable—Set to enable interrupt assertion due to
Data Link FIFO overrun error.
Receive Data Link Message Interrupt Enable— Set to enable interrupt assertion due to a
message received event.
Receive Data Link FIFO Near-Full Interrupt Enable—Set to enable interrupt assertion due to
the FIFO near-full event.
Receive Data Link FCS Check Enable—Set to enable execution of an FCS check on the
received message. When cleared, the FCS check is executed by software; therefore, no
interrupt or status due to bad FCS appears.
Receive Data Link Enable—Set to enable operation of the Receive Data Link FIFO buffer and
HDLC/LAPD circuits over the selected data link channel (Cb5, N-bit, NR, or GC). When
cleared, the data link channel data is left unchanged (may be presented on the data stream via
the REXTCK and RXGAPCK clocks), and no receive datalink interrupts (enabled in this
register) are asserted.
6
6
Transmit Data Link Message Byte (CR15i)
Receive Data Link Control Register (CR16i)
The Receive Data Link Control register enables operation of the receiver terminal data
link circuit, defines the FCS mode, and enables interrupt assertion due to data link
events.
NOTE:
TxDLMsg[5]
NRDL
5
5
Mindspeed Technologies™
Reserved bits in control registers must be set to zero.
TxDLMsg[4]
RxOVRIE
4
4
TxDLMsg[3]
RxMsgIE
3
3
TxDLMsg[2]
RxNFIE
2
2
TxDLMsg[1]
RxFCSEn
1
1
TxDLMsg[0]
RxDLEn
0
0
Registers
3
-
25