CX28344 Conexant, CX28344 Datasheet - Page 63

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
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NOTE:
MA PT—(payload type) Bits 3 to 5 of the MA byte are the payload type field. The
3-bit payload type pattern, to be transmitted, is contained in bits FEBEC/PT[1:3]
at the Feature1 Control register. Writing a new payload type to the register affects
the next transmitted frame.
MA PD/MI—Bits 6 and 7 of the MA byte are the payload dependent/multiframe
indicator bits. There are two modes of operation for these bits: SSM mode, and the
normal mode. When bit SSMEn in Feature4 (I) Control register is set to 1, SSM
mode is enabled. In this mode the MA PD/MI bits act as multiframe indicator bits
(MI). They can be supplied by either an external circuit on TEXT bit input or they
can be automatically generated internally by setting of bit ExtFEAC/PD (when set
to 0, it is automatically generated; when set to 1, it is supplied through the TEXT
pin). When multiframe indication bits are supplied automatically, a 2-bit roll-over
counter is implemented. The counter is incremented each frame and its value is
transmitted on MI bits (The MI counter is reset to 00 when enabling automatic
generation of MI bit in SSM mode). When bit SSMEn is set to 0, SSM mode is
disabled and the PD/MI bits act as the payload dependent bits. When SSM mode is
not set, those bits can be either supplied by external circuitry on the TEXT pin by
setting bit ExtFEAC/PD bit in the Transmit Overhead Insertion 1 register to 1, or
the value to be transmitted can be taken from bits MAPD [1:2] in register Feature4
(I) Control register by setting bits ExtFEAC/PD and SSMEn to 0.
MA TM/SSM—Bit 8 of the MA byte is the timing marker/SSM bit. There are two
modes of operation for these bits: SSM mode, and the normal mode that is
controlled by the settings of bit SSMEn in Feature4 (I) Control register. If bit
SSMEn is set to 1, SSM mode is enabled, otherwise SSM mode is disabled. In
both SSM and normal mode, the bits to be transmitted are written to the register.
When SSM mode is disabled, the TM value to be transmitted is taken from bit
SSM [1]/TM in Feature4 Control register. When SSM mode is enabled, the 4-bit
SSM message to be transmitted is stored in bits SSM [1]/TM, SSM [2:4] in
Feature4 Control register. In this mode, the bit of the SSM message to be
transmitted is selected according to the value of MI transmitted bits (supplied
through the TEXT pin or automatically generated).
NR (DL)—The network operator byte source is determined by bits DLMod [2],
DLMod [1], and DLMod [0] at the Transmit Overhead Insertion 1 Control
register. It can be supplied externally on TEXT. It can be transmitted as all-1s
(data link disabled). The framer is also capable of implementing LAPD data link
using an internal FIFO buffer, as specified in
GC (DL)—The general purpose communication channel bytes source is
determined by bits DLMod [2], DLMod [1] and DLMod [0] at the Transmit
Overhead Insertion 1 Control register together with the NR byte. It can be supplied
externally on the TEXT pin or transmitted as all-1s (data link disabled). The
framer is also capable of implementing an LAPD data link using an internal FIFO
buffer, as specified in
Mindspeed Technologies™
There are eight options for setting NR and GC sources using the DLMod [2:0] bits
setting at the Transmit Overhead Insertion 1 Control register in a E3-G.832 mode of
operation. All are specified in the control register section. The framer is capable of
implementing one LAPD data link using an internal FIFO buffer at a time. In E3-G.832 mode a
LAPD data link can either be implemented on GC or NR, but not on both at the same time.
Section 2.
Section 2.
Functional Description
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