CX28344 Conexant, CX28344 Datasheet - Page 119

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
3.3
Default after reset: 00(h)
Direction: Read/Write
Modification: Dynamic
Chnl4E
Chnl3E
Chnl2E
Chnl1E
Chnl4IntE
Chnl3IntE
Chnl2IntE
Chnl1IntE
28348-DSH-001-B
Chnl4E
7
Channel 4 Enable Control—A general enable control for channel 4. Setting this bit enables
channel 4 for normal operation. Clearing this bit disables channel 4.
Channel 3 Enable Control—A general enable control for channel 3. Setting this bit enables
channel 3 for normal operation. Clearing this bit disables channel 3.
Channel 2 Enable Control—A general enable control for channel 2. Setting this bit enables
channel 2 for normal operation. Clearing this bit disables channel 2.
Channel 1 Enable Control—A general enable control for channel 1. Setting this bit enables
channel 1 for normal operation. Clearing this bit disables channel 1.
Channel 4 Interrupt Enable Control—A general interrupt enable for Channel 4. When cleared,
any interrupt resulting from events in channel 4 are disabled and is not asserted on INTR* pin.
When set, interrupts occurring due to events in channel 4 are asserted on INTR* pin,
depending on the status of the specific event interrupt enable control bit.
Channel 3 Interrupt Enable Control—The same behavior as Chnl4IntE applied to channel 3.
Channel 2 Interrupt Enable Control— The same behavior as Chnl4IntE applied to channel 2.
Channel 1 Interrupt Enable Control—The same behavior as Chnl4IntE applied to channel 1.
Chnl3E
Control Registers
6
General Control Registers
The General Control registers provide for enabling and disabling channels and
interrupts.
General1 Control Register (GCR00)
NOTE:
Chnl2E
5
Mindspeed Technologies™
Reserved bits in the Control registers must be set to zero.
Chnl1E
4
Chnl4IntE
3
Chnl3IntE
2
Chnl2IntE
1
Chnl1IntE
0
Registers
3
-
7