CX28344 Conexant, CX28344 Datasheet - Page 108

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.4
Figure 2-19. Loopback Types
2.4.1
2-62
Loopback
Source
Loopbacks
Shallow Line Loopback
Decoder
Encoder
Shallow
Line
Loop
The Framer provides a complete set of loopbacks for diagnostics, maintenance, and
troubleshooting of each channel. All loopbacks perform clock and data switching, if
necessary. The activation and deactivation of a specific loopback are done through
programmable control bits. Since activation and deactivation of a loopback cause
internal circuits to switch between clocks, after writing to a loopback control bit, the
microprocessor should not access any of the device registers (read or write) for the 20
slowest clock cycles.
The shallow line loopback loops the receiver inputs before B3ZS/HDB3 decoding
back to the line through the transmitter outputs. The shallow line loopback provides
LCV transparency, i.e., LCVs are transmitted exactly as received. The receiver data
path is not affected by activation of this loopback and the received data is still present
on RXDAT pin (it can be replaced by an all-1s or AIS stream by programming RxAll1
or RxAIS bits in Feature5 Control register).
The entire transmitter circuit works with the receiver clock (LINECK); therefore, the
system interface clock outputs (TXGAPCK and TEXTCK) cannot be related to
TXCKI in this mode and are inactive. TXSY is also inactive. If TXSY is programmed
as an input, it is ignored by the transmitter. If TXSY is programmed as an output, it is
blocked by the transmitter. Error insertion on the looped frame is not valid.
When TxLOS bit in Feature2 Control register is set, an all-0s signal is output on the
transmitter and overrides the content of the frame looped from the receiver.
Activation of this loopback is done by setting LineLp bit in the Mode Control register.
When the receiver and the transmitter are programmed to be in shallow line loopback,
and the line code is set to unipolar (NRZMod bit in Feature Control register is set),
TXNEG output pin is forced to 0. Therefore, TXNEG does not reflect RXNEG in
unipolar mode.
NOTE:
Mindspeed Technologies™
The Shallow line loopback and source loopback cannot be operated simultaneously.
Remote Line
Loopback
Dejitter
FIFO
Rx
Transmitter
Receiver
Loopback
Payload
CX28342/3/4/6/8 Data Sheet
100542_022
28348-DSH-001-B