CX28344 Conexant, CX28344 Datasheet - Page 105

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.3.4
2.3.5
28348-DSH-001-B
Hardware Reset
Software Reset
about which channel is responsible for interrupt generation. The General1 Control
register enables masking the complete set of interrupts of a channel by clearing one
bit.
Using these registers, the microprocessor processes interrupts as follows:
The only exception in the Source Channel Status register is OneSecItr Status bit. This
bit always reflects the status of OneSec Counter regardless of the state of its mask.
INTR*, however, becomes active due to the OneSec Counter roll-over only if the
interrupt is enabled (by One SecIE bit).
Assertion of the hardware reset (RESET*) places internal registers into their default
power-up state. Asserting RESET* is required because there is no other way to put the
device into reset state. RESET* is used as a level signal. During RESET*, the system
and line clocks are supplied for at least 30 cycles, to put the registers into their default
values. LINECK and TXCKI must always be supplied in RESET*. RXCKI is
supplied if the receive dejitter FIFO buffer is used in the future. During RESET* the
system side outputs (besides VCO) are High-Z. The transmitter line side interface is
as follows: TCLKO is active and reflects TXCKI; TXPOS and TXNEG are forced to
be zero. During RESET* VCO output is active.
After RESET* all the channels are disabled and the control registers set to their
default values (the defaults are described in
microprocessor must initialize the control registers to the desired state and enable the
channels that are to be operational.
Assertion of software reset affects the device in the same way as hardware reset.
Setting SWRst bit in General2 Control register activates a software reset. The bit is
cleared automatically by the device when all internal circuits are reset and when
internal registers are at their default values.
During software reset, system interface pins (besides VCO) continue to be active, and
when control registers are set to their default values, the pins behave accordingly.
Transmitter line side interface and VCO outputs behave similarly to hardware reset.
NOTE:
1.
2.
3.
4.
Read Source Channel Status register to determine which channels caused the
interrupt.
For each interrupting channel, read Interrupt Source Status register to determines
which status registers contain the interrupt events.
Read the status registers to determine which events caused the interrupt.
Enter the appropriate service routine.
Mindspeed Technologies™
In exceptional cases, the microprocessor can identify an interrupt, and due to a delay
and other actions taken prior to reading the relevant status register, the status bit
indicating the interrupt source is already cleared. In such cases, the source of the
interrupt might be unknown.
Chapter
3). After hardware RESET*, the
Functional Description
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