CX28344 Conexant, CX28344 Datasheet - Page 151

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Value after reset: Undefined
Direction: Read only
Value after enable: Undefined
RxDLMsg[7:0]
28348-DSH-001-B
RxDLMsg[7]
RxDLMsg[7]
RxDLMsg[7]
Type Select
Undefined
7
RxDLMsg[6]
RxDLMsg[6]
RxDLMsg[6]
Undefined
Length[6]
Receive Data Link Message Byte—This register is used to read the content of the Receive
Data Link FIFO. Issuing a receive FIFO read is done by addressing this register, which results
in putting the byte read from the FIFO on the microprocessor data bus. The type of this
register’s content (status or data) is defined by StatByte bit in the Receive Data Link Status
register or as described in the Terminal Data Link Reception paragraph.
The receive order of bits from the line is RxDLMsg[0] bit is received first and RxDLMsg[7]
bit is received last from the line. When this register contains data it can be any combination of
1s and 0s. When this register contains a status, it defines the status of the following data block,
where the 1 MS bits contain the block’s type (correct or partial) for a good block, or undefined
for errored block. The other 7 bits are used as length field or error indications.
For RxGoodBlk-set the register contains:
RxDLMsg[7]: set for complete, cleared for partial.
For RxGoodBlk cleared, the register contains the following block, illustrating the content of
the status register in incorrect-end-of-message state and details the different error indications
that can be set.
The error indications are:
6
Receive Data Link Message Byte (SR12i)
!
!
!
!
Only one error type is set according to this priority: OVR, Abort, AlignErr, BadFCS
(highest to lowest).
NOTE:
RxDLMsg[5]
RxDLMsg[5]
Abort—When an abort sequence is detected, the message is terminated and the bit
set.
OVR—When an overrun error happens (FIFO buffer is full and a new byte was
received), the message is terminated and the bit set.
AlignErr—When the number of bits in the message is indivisible by 8 (alignment
error), the message is terminated and the bit set.
BadFCS—When there is a mismatch between the calculated and the received FCS,
the message is terminated and the bit set.
RxDLMsg[5]
Length[5]
Undefined
5
Mindspeed Technologies™
The length of the following block is always considered as 0, and only one indication
can be set at a time.
RxDLMsg[4]
RxDLMsg[4]
RxDLMsg[4]
Undefined
Length[4]
4
RxDLMsg[3]
RxDLMsg[3]
RxDLMsg[3]
Length[3]
Abort
3
RxDLMsg[2]
RxDLMsg[2]
RxDLMsg[2]
Length[2]
OVR
2
RxDLMsg[1]
RxDLMsg[1]
RxDLMsg[1]
Length[1]
AlignErr
1
RxDLMsg[0]
RxDLMsg[0]
RxDLMsg[0]
Length[0]
BadFCS
0
Registers
3
-
39