CX28344 Conexant, CX28344 Datasheet - Page 94

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.2.5.9
2.2.5.10
2.2.5.11
2.2.6
2-48
One-Second Counter Latching
Path Parity Error (PPER)
In DS3 C-bit parity mode, the PPER event is declared when at least two of the three
Cb3 bits differ in value from the expected value as calculated from the previous
frame. The PPER event increments the PPER counter.
If the ExtFEBE/Cj field of the TransmitOverheadInsertion 1 Control register is
enabled, FEBE gets transmitted on the transmit stream upon a PPER event.
Remote Alarm/Defect Indication (RAI/RDI), X-bit disagreement (XBD)
In DS3, an RAI/RDI event is declared when both X-bits of a receive frame are 0. The
RAI/RDI event is terminated when both X-bits are 1. The XBD event is declared
when the two X-bits are not equal.
In E3, an RAI/RDI event is declared when two consecutive receive frames have an A/
RDI bit with the value 1. The RAI/RDI event is terminated when two consecutive
frames have an A/RDI bit with the value 0. The XBD event is not defined.
The RAI/RDI even generates a YelStrt interrupt indication and sets the YelDet status
indication bit in the Maintenance Status register. Upon terminating, the RAI/RDI
event generates a YelEnd interrupt indication and clears the YelDet status indication
bit. The XBD event increments the XBD counter.
Far-End Block Error/Remote Error Indication (FEBE/REI)
The FEBE/REI event is defined only in DS3 C-bit parity mode and E3-G.832 mode.
In DS3 C-bit parity mode, it is declared when at least one of the three Cb4 bits is 0. In
E3-G.832 mode, it is declared when the REI-bit is 1. The FEBE/REI event increments
the FEBE/REI counter.
A special mode simplifies reading counters every second. Setting the OneSecMod
field in the General2 register, activates this mode. On every second in this mode, the
values in the performance monitoring counters latch into shadow counters (upon the
rising edge of the OneSec trigger), and the original counters reset to 0. This is
accompanied by the setting of the OneSecItr field in source channel and, if the
1SecTimIE field in General2 Control register is set, by an interrupt. When counters
are read in this mode, the value returned is always from the shadow counters.
The one-second trigger for latching is one of two ways:
NOTE:
1.
2.
If the ONESEC pin is set to output (via the OneSecOut field in the General2
register), it is based on a one-second counter (OneSecCtr) incremented by
channel 1’s TXCKI, (the value to count is determined by software) and is
accompanied by an outgoing 16-clock-long pulse on the ONESEC pin
If the ONESEC pin is set to input (via the OneSecIn field in the General2
register), it is based on an incoming pulse on the ONESEC pin.
Mindspeed Technologies™
Writing to the counters does not trigger latching. To function properly, the counters
must be set to saturating mode by clearing all counter interrupt enable bits in the
Counter Interrupt Control register. While the channel is disabled, the one second
latching operation is also disabled. When counters are read while the mode is on and
channel is disabled, the value returned is the one latched prior to disabling the channel.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B