LPC2468FBD208,551 NXP Semiconductors, LPC2468FBD208,551 Datasheet - Page 119

• Manufacturer Part Number: LPC2468FBD208,551
• Description: IC ARM7 MCU FLASH 512K 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4261; 935282457551; LPC2468FBD208-S

NXP Semiconductors
UM10237_4
User manual
Fig 22. Block diagram of the Vectored Interrupt Controller
IRQStatus
IRQStatus
IRQStatus
SOURCE
VICINT
[31:0]
[31]
[0]
[1]
interrupt request, masking, and selection
vectored interrupt 0
HWPriorityMask [0]
vectored interrupt 1
vectored interrupt 31
SWPriorityMask [0]
SoftIntClear
D
VectPriority0
RawIntr
SoftInt
[31:0]
[31:0]
[31:0]
Q
[3:0]
D
Q
IntEnableClear
PRIORITY
MASKING
VectAddr0
LOGIC
[31:0]
IntEnable
IntSelect
[31:0]
[31:0]
[31:0]
Rev. 04 — 20 August 2009
VectIRQ31
Vect Addr31
Vect Addr0
Vect Addr1
VectIRQ0
VectIRQ1
[31:0]
[31:0]
[31:0]
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
HWPriorityMask [31:0]
SWPriorityMask [31:0]
IRQStatus
FIQStatus
[31:0]
[31:0]
status registers and FIQ generation
IRQStatus
prioritization and vector generation
FIQStatus
[31:0]
[31:0]
PRIORITY
LOGIC
SWPriorityMask
[31:0]
vector select
for highest priority
interrupt
VectAddr
[31:0]
UM10237
© NXP B.V. 2009. All rights reserved.
AddrOut
IRQ
FIQ
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Vect